PIC18F2331-E/ML MICROCHIP [Microchip Technology], PIC18F2331-E/ML Datasheet - Page 201
PIC18F2331-E/ML
Manufacturer Part Number
PIC18F2331-E/ML
Description
28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2331-EML.pdf
(392 pages)
- Current page: 201 of 392
- Download datasheet (4Mb)
REGISTER 18-8:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
BRFEN
R/W-0
2:
Unimplemented in PIC18F2331/2431 devices; maintain these bits clear.
PWM<7:6> are implemented only on PIC18F4331/4431 devices. On PIC18F2331/2431 devices, setting or
clearing FLTCON has no effect.
BRFEN: Breakpoint Fault Enable bit
1 = Enable Fault condition on a breakpoint (i.e., only when PWMPIN = 1)
0 = Disable Fault condition
FLTBS: Fault B Status bit
1 = FLTB is asserted:
0 = No Fault
FLTBMOD: Fault B Mode bit
1 = Cycle-by-Cycle mode: Pins are inactive for the remainder of the current PWM period or until FLTB
0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTB is deasserted and FLTBS is
FLTBEN: Fault B Enable bit
1 = Enable Fault B
0 = Disable Fault B
FLTCON: Fault Configuration bit
1 = FLTA, FLTB or both deactivates all PWM outputs
0 = FLTA or FLTB deactivates PWM<5:0>
FLTAS: Fault A Status bit
1 = FLTA is asserted:
0 = No Fault
FLTAMOD: Fault A Mode bit
1 = Cycle-by-Cycle mode: Pins are inactive for the remainder of the current PWM period or until FLTA is
0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTA is deasserted and FLTAS is
FLTAEN: Fault A Enable bit
1 = Enable Fault A
0 = Disable Fault A
FLTBS
R/W-0
if FLTBMOD = 0, cleared by the user;
if FLTBMOD = 1, cleared automatically at beginning of the new period when FLTB is deasserted
is deasserted; FLTBS is cleared automatically when FLTB is inactive (no Fault present)
cleared by the user only
if FLTAMOD = 0, cleared by the user;
if FLTAMOD = 1, cleared automatically at beginning of the new period when FLTA is deasserted
deasserted; FLTAS is cleared automatically
cleared by the user only
FLTCONFIG: FAULT CONFIGURATION REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
FLTBMOD
R/W-0
(1)
(1)
(1)
(1)
PIC18F2331/2431/4331/4431
FLTBEN
(2)
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FLTCON
R/W-0
(2)
FLTAS
R/W-0
x = Bit is unknown
FLTAMOD
R/W-0
DS39616D-page 201
FLTAEN
R/W-0
bit 0
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