ADAU1590ASVZ AD [Analog Devices], ADAU1590ASVZ Datasheet - Page 19

• Manufacturer Part Number: ADAU1590ASVZ
• Description: Class-D Audio Power Amplifier
• Manufacturer: AD [Analog Devices]

To shut down the power supplies, it is highly recommended to
mute the amplifier before shutting down any of the supplies.
After MUTE is shut down, shut down the supplies in the follow-
ing order: PVDD, DVDD, then AVDD. Where AVDD and
DVDD are generated from a single source, turn PVDD off
before DVDD and AVDD, and after issuing MUTE .
DC OFFSET AND POP NOISE
This section describes the cause of dc offset and pop noise
during turn-on/turn-off. The turn-on/turn-off pop in
amplifiers depend mainly on the dc offset, therefore, care must
be taken to reduce the dc offset at the output.
The first stage of ADAU1590 has an inverting PGA amplifier, as
shown in Figure 45.
where:
R
R
setting).
R
C
C
V
V
As shown in Figure 45, the dc offset at the output can be due to
V
leakage current of the C
Normally, the offset due to leakage current in the C
can be ignored compared to V
ble for the dc offset at the output. The ADAU1590 uses special
self-calibration or a dc offset trim circuit, which controls the dc
offset (due to V
part as well as for voltage and temperature. The trim circuit
ensures that the offset is limited within specified limits and
provides virtually pop-free operation every time the part is
turned on. However, care must be taken while unmuting or
during the power-up sequence.
During the initial power-up, C
AVDD/2 and, during this time, there can be dc offset at the
output (see Figure 45). This depends on the PGA gain setting.
The dc offset is multiplied by the PGA gain setting. If the
amplifier is kept in mute during this charging and self-trimming
event for the recommended t
output remains within ±3 mV. For more details on t
to the Power-Up/Power-Down Sequence section.
IN
FB
SOURCE
IN
REF
REF
MIS
MIS
= 20 kΩ, fixed internally.
is the gain feedback resistor (value depends on the PGA
is the input coupling capacitor (2.2 μF typical).
is the filter capacitor for V
is the analog reference voltage (AVDD/2 typical).
is the dc offset due to mismatch in the op amp.
(the dc offset from mismatch in the op amp) and due to
is the source resistance.
R
SOURCE
C
MIS
C
IN
REF
Figure 45. Input Equivalent Circuit
) to within ±3 mV. The V
AINx
V
REF
CHANGES WITH PGA SETTING
IN
R
capacitor.
IN
WAIT
MIS
V
IN
REF
MIS
. The V
and C
time, the dc offset at the
.
R
FB
REF
TO NEXT STAGE
MIS
are charging to
is mainly responsi-
MIS
can vary for each
IN
WAIT
is less and
, refer
Rev. 0 | Page 19 of 24
The amount of pop at the turn-on depends on t
turn depends on the values of C
section describes how to select the value for the C
SELECTING VALUE FOR C
The C
AVDD on V
analog amplifier as well as the modulator. Therefore, care must
be taken to ensure that the recommended minimum value is
used. The minimum recommended value for C
C
inputs from the external dc. The C
corner frequency of the amplifier. It can be determined from
the following equation:
where:
f
R
C
Note that R
is sizable with respect to R
in calculation.
From the preceding equation, f
frequency response.
The recommended value for C
and should keep 20 Hz roll-off within −0.5 dB.
However, if a higher than recommended C
better low frequency response, care must be taken to ensure
that appropriate t
Sequence section for more details.
MONO MODE
The ADAU1590 mono mode can be enabled by pulling MO/ ST
(Pin 11) to logic high. In this mode, the left channel input and
modulator is active and feeds PWM data to both the left and
right power stages. However, the respective power FETs need to
be connected externally for higher current capability. That is,
connect OUTL+ with OUTR+ and OUTL− with OUTR−. The
mono mode gives the capability to drive lower impedance loads
without invoking current limit. However, the output power is
limited by PVDD and temperature limits. See the typical applica-
tion schematic in Figure 47 for details.
POWER SUPPLY BYPASSING
Because Class-D amplifiers utilize high frequency switching,
care must be taken to bypassing the power supply.
For reliable operation, using 100 nF ceramic surface-mount
capacitors for the PVDD and PGND pins is recommended. The
minimum of two capacitors are needed: one between Pin 45/Pin 46
(PVDD) and Pin 47/Pin 48 (PGND), the other between Pin 39/
Pin 40 (PVDD) and Pin 37/Pin 38 (PGND). In addition, these
LOW
IN
IN
IN
is the input resistance (20 kΩ).
is the input coupling capacitor.
is the input coupling capacitor and is used to decouple the
is the low corner frequency (−3 dB).
f
REF
LOW
is the capacitor used for filtering the noise from
=
IN
REF
2
= 20 kΩ, provided that R
×
. V
π
WAIT
REF
×
R
1
is used for the biasing of the internal
IN
is used. See the Power-Up/Power-Down
×
C
IN
IN
, it also must be taken into account
IN
LOW
REF
REF
is 2.2 μF, giving f
IN
and C
can be found for the desired
AND C
value determines the low
SOURCE
IN
. The following
IN
IN
is <1 kΩ. If R
value is used for
REF
WAIT
ADAU1590
LOW
REF
is 4.7 μF.
, which in
and C
= 3.6 Hz,
SOURCE
IN
.