AIC1571 AIC [Analog Intergrations Corporation], AIC1571 Datasheet - Page 10

• Manufacturer Part Number: AIC1571
• Description: 5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers
• Manufacturer: AIC [Analog Intergrations Corporation]

DESCRIPTION
The POR function initiates the soft-start se-
quence. Initially, the voltage on SS pin rapidly
increases to approximate 1V. Then an internal
10µA current source charges an external ca-
pacitor (C
voltage slews from 1V to 4V, the PWM error
amplifier reference input (Non-inverting termi-
nal) and output (COMP1 pin) is clamped to a
level proportional to the SS pin voltage. As the
The AIC1571 is designed for microprocessor
computer applications with 3.3V and 5V power,
and 12V bias input. This IC has one PWM
controller and two linear controllers. The PWM
controller is designed to regulate the micro-
processor core voltage (V
MOSFETs (Q1 and Q2) in a synchronous recti-
fied buck converter configuration. The core
voltage is regulated to a level programmed by
the 5 bit D/A converter. One integrated linear
controller supplies the 2.5V clock power (V
The other linear controller drive an external
MOSFET(Q3)
power(V
The Power-On Reset (POR) function continu-
ally monitors the input supply voltage +12V at
VCC pin, the 5V input voltage at OCSET pin,
and the 3.3V input at VIN2 pin. The POR func-
tion initiates soft-start operation after all three
input supply voltage exceed their POR thresh-
olds.
Soft-Start
OUT3
SS
) on the SS pin to 4V. As the SS pin
)
to
supply
OUT1
the
) by driving 2
GTL
OUT2
bus
).
Fault Protection
SS pin voltage slew from 1V to 4V, the output
clamp generates PHASE pulses of increasing
width that charge the output capacitors. Addi-
tionally both linear regulator’s reference inputs
are clamped to a voltage proportional to the SS
pin voltage. This method provides a controlled
output voltage smooth rise.
Fig.4 and Fig.5 show the soft-start sequence
for the typical application. The internal oscilla-
tor’s triangular waveform is compared to the
clamped error amplifier output voltage. As the
SS pin voltage increases, the pulse width on
PHASE pin increases. The interval of increas-
ing pulse width continues until output reaches
sufficient voltage to transfer control to the input
reference clamp.
Each linear output (VOUT2 and VOUT3) ini-
tially follows a ramp. When each output
reaches sufficient voltage the input reference
clamp slows the rate of output voltage rise. The
PGOOD signal toggles ‘high’ when all output
voltage levels have exceeded their under-
voltage levels.
All three outputs are monitored and protected
against extreme overload. A sustained over-
load on any output or over-voltage on PWM
output disable all converters and drive the
FAULT pin to VCC.
AIC1571
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