AIC1571 AIC [Analog Intergrations Corporation], AIC1571 Datasheet - Page 11

• Manufacturer Part Number: AIC1571
• Description: 5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers
• Manufacturer: AIC [Analog Intergrations Corporation]

A simplified schematic is shown in figure 17. An
over-voltage detected on VSEN immediately
sets the fault latch. A sequence of three over-
current fault signals also sets the fault latch. An
under-voltage event on either linear output
(FB2 or FB3) is ignored until the soft-start inter-
val. Cycling the bias input voltage (+12V) off
then on reset the counter and the fault latch.
Over-Voltage Protection
All outputs are protected against excessive
over-current. The PWM controller uses upper
MOSFET’s on-resistance, R
the current for protection against shorted out-
puts. Both the linear regulator and controller
monitor FB2 and FB3 for under-voltage to pro-
During operation, a short on the upper PWM
MOSFET (Q1) causes V
the output exceed the over-voltage threshold of
115% of DACOUT, the FAULT pin is set to
fault latch and turns Q2 on as required in order
to regulate V
fault latch raises the FAULT pin close to VCC
potential.
A separate over-voltage circuit provides pro-
tection during the initial application of power.
For voltage on VCC pin below the power-on re-
set (and above 4V), should VSEN exceed 0.7V,
the lower MOSFET (Q2) is driven on as need-
ed to regulate V
Over-Current Protection
OUT1
OC1
0.2V
LUV
3.6V
SS
OV
OUT1
to 115% of DACOUT. The
to 0.7V.
+
+
OUT1
to increase. When
DS(ON)
OVER CURRENT
Fig. 17 Simplified Schematic of Fault Logic
R
S
LATCH
to monitor
Q
POR
INHIBIT
COUNTER
R
S
tect against excessive current.
When the voltage across Q1 (I
ceeds the level (200µA•R
hibit all outputs. Discharge soft-start capacitor
(Css) with 10µA current sink, and increments
the counter. Css recharges and initiates a soft-
start cycle again until the counter increments to
3. This sets the fault latch to disable all outputs.
Fig. 6 illustrates the over-current protection un-
til an over load on OUT1.
Should excessive current cause FB2 or FB3 to
fall below the linear under-voltage threshold,
the LUV signal sets the over-current latch if
Css is fully charged. Cycling the bias input
power off then on reset the counter and the
fault latch.
The over-current function for PWM controller
will trip at a peak inductor current (I
mined by:
The OC trip point varies with MOSFET’s tem-
perature. To avoid over-current tripping in the
normal operating load range, determine the
R
1. The maximum R
2. The minimum I
OCSET
FAULT LATCH
S
R
resistor from the equation above with:
Q
I
PEAK
VCC
=
OCSET
DS(ON)
I
FAULT
OCSET
R
at the highest junction.
from the specification
DS(ON)
×
OCSET
R
OCSET
AIC1571
), this signal in-
D
•R
PEAK
DS(ON)
) deter-
11
) ex-