PIC18F2510-E/P MICROCHIP [Microchip Technology], PIC18F2510-E/P Datasheet - Page 301

• Manufacturer Part Number: PIC18F2510-E/P
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

CALLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC
PCLATH =
PCLATU =
W
PC
TOS
PCLATH =
PCLATU =
W
Q1
=
=
=
=
=
operation
Subroutine Call Using WREG
CALLW
None
(PC + 2) → TOS,
(W) → PCL,
(PCLATH) → PCH,
(PCLATU) → PCU
None
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a
new next instruction is fetched.
Unlike
update W, STATUS or BSR.
1
2
HERE
WREG
Read
0000
No
Q2
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
CALL
CALLW
0000
Push PC to
, there is no option to
operation
NOP
stack
No
Q3
instruction while the
0001
operation
operation
No
No
Q4
0100
MOVSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
PIC18F2X1X/4X1X
Decode
Decode
FSR2
Contents
of 85h
REG2
FSR2
Contents
of 85h
REG2
Q1
source addr
No dummy
Determine
operation
Move Indexed to f
MOVSF [z
0 ≤ z
0 ≤ f
((FSR2) + z
None
The contents of the source register are
moved to destination register ‘f
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
2
2
MOVSF
d
read
’ in the second word. Both addresses
1110
1111
No
Q2
=
=
=
=
=
=
d
s
≤ 4095
≤ 127
s
’ in the first word to the value of
80h
33h
11h
80h
33h
33h
[05h], REG2
s
s
source addr
1011
ffff
], f
) → f
Determine
operation
d
No
Q3
DS39636D-page 303
d
0zzz
ffff
source reg
register ‘f’
(dest)
Read
Write
d
Q4
ffff
zzzz
’. The
s
d