MC68HC908GZ8 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GZ8 Datasheet - Page 205

• Manufacturer Part Number: MC68HC908GZ8
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits
SCR2–SCR0 — ESCI Baud Rate Select Bits
Freescale Semiconductor
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The
break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
These read/write bits select the baud rate register prescaler divisor as shown in
clears SCP1 and SCP0.
These read/write bits select the ESCI baud rate divisor as shown in
SCR2–SCR0.
LINT
0
0
0
1
1
1
1
LINR
0
1
1
0
0
1
1
SCP[1:0]
SCR[2:1:0]
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
0 0
0 1
1 0
1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 15-7. ESCI Baud Rate Prescaling
Table 15-8. ESCI Baud Rate Selection
M
Table 15-6. ESCI LIN Control Bits
X
0
1
0
1
0
1
Normal ESCI functionality
13-bit break detect enabled for LIN receiver
14-bit break detect enabled for LIN receiver
13-bit generation enabled for LIN transmitter
14-bit generation enabled for LIN transmitter
13-bit break detect/11-bit generation enabled for LIN
14-bit break detect/12-bit generation enabled for LIN
Prescaler Divisor (BPD)
Baud Rate Divisor (BD)
Baud Rate Register
Functionality
13
1
3
4
128
16
32
64
1
2
4
8
Table
15-8. Reset clears
Table
15-7. Reset
I/O Registers
205