MC68HC908GZ8 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GZ8 Datasheet - Page 80

• Manufacturer Part Number: MC68HC908GZ8
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Configuration Register (CONFIG)
MSCANEN— MSCAN08 Enable Bit
TMCLKSEL— Timebase Clock Select Bit
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
ESCIBDSRC — SCI Baud Rate Clock Source Bit
COPRS — COP Rate Select Bit
80
Setting the MSCANEN enables the MSCAN08 module and allows the MSCAN08 to use the PTC0/PTC1
pins. See
MSCAN08 operation.
TMCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it. See
a more detailed description of the external clock operation.
OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module
the reset of the MCU stops. See
to generate clocks while in stop mode. The default state for this option is clear, disabling the oscillator
in stop mode.
ESCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting
of this bit affects the frequency at which the SCI operates.See
Communications Interface (ESCI)
COPD selects the COP timeout period. Reset clears COPRS. See
Properly (COP) Module
1 = Enables MSCAN08 module
0 = Disables the MSCAN08 module
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
1 = Internal data bus clock used as clock source for SCI (default)
0 = External oscillator used as clock source for SCI
1 = COP timeout period = 2
0 = COP timeout period = 2
Note: LVI5OR3 bit is only reset via POR (power-on reset).
Address:
Reset:
Read:
Write:
Chapter 12 MSCAN08 Controller (MSCAN08)
The MSCANEN bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
COPRS
$001F
Bit 7
0
Figure 5-2. Configuration Register 1 (CONFIG1)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
LVISTOP
6
0
13
18
Chapter 18 Timebase Module
– 2
– 2
Module.
LVIRSTD
(CGM). This function is used to keep the timebase running while
4
4
5
0
COPCLK cycles
COPCLK cycles
LVIPWRD
NOTE
4
0
LVI5OR3
See note
Chapter 4 Clock Generator Module (CGM)
for a more detailed description of the
3
(TBM). When clear, oscillator will cease
Chapter 15 Enhanced Serial
SSREC
2
0
Chapter 6 Computer Operating
STOP
1
0
Freescale Semiconductor
COPD
Bit 0
0
for