DP8473N NSC [National Semiconductor], DP8473N Datasheet - Page 3

• Manufacturer Part Number: DP8473N
• Description: DP8473 Floppy Disk Controller PLUS-2
• Manufacturer: NSC [National Semiconductor]

A0 A1 A2
CS
DAK
DIR
DRQ
DRV TYP
DR0
DR1
DR2
DR3
DSKCHG RG
D0 –D4
D5 –D7
FGND250
FGND500
FILTER
GNDA
GNDB
GNDC
GNDD
HD SEL
INDEX
INT
Pin Descriptions
Symbol
DP8473
19–21
28–30
22-26
PCC
18
32
31
47
45
43
35
42
41
40
39
27
36
11
34
4
6
5
2
9
DP8473
17–19
20–24
26–28
DIP
16
30
29
43
33
40
39
38
37
25
34
48
32
2
4
3
7
9
Address lines from the microprocessor This determines which registers the
microprocessor is accessing as shown in Table IV in the Register Description Section
Don’t care during DMA transfers
Active low input to enable the RD and WR inputs Not required during DMA transfers
This should be held high during DMA transfers
Active low input to acknowledge the DMA request and enable the RD and WR inputs
This signal is enabled when D3 of the Drive Control Register is set
This output determines the direction of the head movement (low
out) When in the write or read modes this output will be high This is a high drive open
drain output
Active high output to signal the DMA controller that a data transfer is needed This signal
is enabled when D3 of the Drive Control Register is set
This is an input used by the controller to enable the 300 kb s mode This enables the use
of floppy drives with either dual or single speed spindle motors For dual speed spindle
motors this pin is tied low When low and 300 kb s data rate is selected in the data rate
register the PLL actually uses 250 kb s This pin is tied high for single speed spindle
motor drives (standard AT drive) When this pin is high and 300 kb s is selected 300 kb s
is used (See also RPM LC pin)
This is an active low drive select line for drive 0 that is controlled by the Drive Control
register bits D0 D1 The Drive Select bit is ANDed with the Motor Enable of the same
number This is a high drive open drain output
This is an active low drive select similar to DR0 line except for drive 1
This is the same as DR0 except for drive 2
This is the same as DR0 except for drive 3
This latched Schmitt input signal is inverted and routed to D7 of the data bus and is read
when address xx7H is enabled DSKCHG is a disk drive output that indicates when the
drive door has been opened When the RG bit in the Mode Command is set this pin
functions as a Read Gate signal that when low forces the data separator to lock to the
crystal and when high it locks to data for diagnostic purposes
Bi-directional data lines to the microprocessor These are the lower 5 bits and have
buffered 12 mA outputs
Bi-directional data lines to the microprocessor These upper 3 bits have buffered 12 mA
outputs
This pin connects the PLL filter for 250k(MFM) 125k(FM) b s or 300k(MFM) 150k(FM)
b s to ground This is a low impedance open drain output
This pin connects the PLL filter for 500k(MFM) 250k(FM) b s to ground This is a low
impedance open drain output
This pin is the output of the charge pump and the input to the VCO One or more filters
are attached between this pin and the GNDA FGND250 and FGND500 pins
This pin is the analog ground for the data separator including all primary and secondary
PLLs and delay lines
This pin is the digital ground for the 12 mA microprocessor interface buffers This
includes D0 – D7 INT and DRQ
This pin is the digital ground for the controller’s digital logic including all internal registers
micro-engine etc
This pin is the digital ground for the disk interface output drivers
This output determines which disk drive head is active Low
Head 0 This is a high drive open drain output
This active low Schmitt input signals the beginning of a track
Active high output to signal that an operation requires the attention of the
microprocessor The action required depends on the current function of the controller
This signal is enabled when D3 of the Drive Control Register is set
3
Function
e
Head 1 Open (high)
e
step in high
e
step
e