DP8473N NSC [National Semiconductor], DP8473N Datasheet - Page 8

• Manufacturer Part Number: DP8473N
• Description: DP8473 Floppy Disk Controller PLUS-2
• Manufacturer: NSC [National Semiconductor]

Functional Description
C
R
C
K
K
The trade off when choosing filter components is between
acquisition time while the PLL is locking and jitter immunity
while reading data To select the proper components for a
standard floppy disk application the following procedure can
be used
1 Choose FM or MFM and data rate Determine N from
Table III Determine preamble length (MFM
should lock within
2 Determine loop bandwidth (
charge pump resistor R
3 Calculate C
4 Choose R
6 Select C
The above procedure will yield adequate loop performance
If optimum loop performance is required or if the nature of
the loop performance is very critical then some additional
consideration must be given to choosing
ing factor (For a detailed description on how to choose
and
Guide for the DP8473)
WRITE PRECOMPENSATION
The DP8473 incorporates a single fixed 3-bit shift register
This shift register outputs are tapped and multiplexed onto
the write data output The taps are selected by a standard
precompensation algorithm This precompensation value
can be selected from the PUMP PREN pin When this pin is
2
2
1
VCO
PLL
n
Filter capacitor in series with R
this determines loop bandwidth
Filter resistor Determines the PLL damping factor
This filter capacitor improves the performance of the
PLL by providing additional filtering of bit jitter and
noise
The ratio of the change in the frequency of the VCO
output due to a voltage change at the VCO input
K
vider to achieve the desired frequency for each data
rate VCO center frequency is 4 MHz for data rates
of 1 Mb s 500 kb s and 250 kb s (MFM) and is
4 8 MHz for 300 kb s (MFM)
This is the gain of the internal PLL circuitry and is
the product of V
specified in the Phase Locked Loop Characteristics
table
This is the bandwidth of the PLL and is given by
where N is the number of VCO cycles between two
phase comparisons The value of N for the various
data rates are shown in Table III
The damping factor is set to 0 7 to 1 2 and is given
by
see AN-505 Floppy Disk Data Separator Design
VCO
1
2
to be about
2
using
using
25 Mrad s V The VCO is followed by a di-
C
the preamble time
2
1
R
REF c
e
n
2
2 R
e
e
th of C
e
K
2
PLL
1
n
K
2 C
N
C
n
VCO c
n
R
2
2
K
) required and set the
2
2
n 2
PLL
2
C
N R
2
2
(Continued)
With pump current
1
K
n
P
e
and the damp-
This value is
12) The PLL
n
8
differences between the 52 pin PLCC and the 48 pin DIP
version are that the MTR2 and 3 and DR2 and 3 pins have
been removed in order to accommodate the 48 pin pack-
age
low 125 ns precomp is used for all data rates except 1 Mb s
which uses 83 ns When PREN is tied high the precompen-
sation-value scales with data rate at 250 kb s its 250 ns for
300 kb s its 208 ns at 500 kb s its 125 ns and at 1 0 Mb s
its 83 ns These values are shown in Table VI
PC-AT AND PC-XT LOGIC BLOCKS
This section describes the major functional blocks of the PC
logic that have been integrated on the controller Refer back
to Figure 1 the block diagram
DMA Enable Logic This is gating logic that disables the
DMA lines and the Interrupt output under the control of the
DMA Enable bit in the Drive control register When the DMA
Enable bit is 0 then the INT and DRQ are held TRI-STATE
and DAK is disabled
Drive Output Buffers Input Receivers The drive inter-
face output pins can drive 150
tors This enables connection to a standard floppy drive All
drive interface inputs are TTL compatible schmitt trigger in-
puts with typically 250 mV of hysteresis The only functional
Bus Interface-Address Decode The address decode cir-
cuit allows software access to the controller Drive Control
Register and Data Rate Register (see Table IV for the
memory map) using the same address map as is used in the
XT AT or PS 2 The decoding is provided for A0– A2 so
only a single address decoder connected to the chip select
is needed to complete the decode The bus interface logic
includes the 8-bit data bus and DRQ INT signals The out-
put drive for these pins is 12 mA
Drive Control Register This 8-bit write only register con-
trols the drive selects motor enables DMA enable and Re-
set See Register Description
Reset Logic The reset input pin is active high and directly
feeds the Drive Control Register and the Data Rate Regis-
ter After a hardware reset the Drive Control Register is re-
set to all zeros and the Data Rate Register is set to
250 kb s data rate The controller is held reset until the
software sets the Drive Control reset bit after which the
controller may be initialized A software reset to the control-
ler core can be issued by resetting then setting this bit A
software reset does not reset the Drive Control Register or
the Data Rate Register
When this location is accessed only bit D7 is driving all others are held
TRI-STATE
A2
0
0
0
0
1
1
1
1
1
TABLE IV Address Memory Map for DP8473
A1
0
0
1
1
0
0
1
1
1
A0
0
1
0
1
0
1
0
1
1
R W
R W
W
W
X
X
X
R
X
R
None (Bus TRI-STATE)
None (Bus TRI-STATE)
Drive Control Register
None (Bus TRI-STATE)
Main Status Register
Data Register
None (Bus TRI-STATE)
Data Rate Register
Disk Changed Bit
g
10% termination resis-
Register