SAB-C167SR-LM SIEMENS [Siemens Semiconductor Group], SAB-C167SR-LM Datasheet - Page 49

• Manufacturer Part Number: SAB-C167SR-LM
• Description: 16-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
AC Characteristics
Multiplexed Bus
V
T
T
T
C
C
ALE cycle time = 6 TCL + 2
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
Semiconductor Group
A
A
A
CC
L
L
= 0 to + 70 ˚C
= – 40 to + 85 ˚C for SAF-C167SR-LM
= – 40 to + 125 ˚C for SAK-C167SR-LM
(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
(for Port 6, CS) = 100 pF
= 5 V
10 %;
V
for SAB-C167SR-LM
SS
= 0 V
t
Symbol
t
t
t
t
t
t
t
t
t
5
6
7
8
9
10
11
12
13
A
+
t
C
CC
CC
CC
CC
CC
CC
CC
CC
CC
+
t
F
(150 ns at 20-MHz CPU clock without waitstates)
Symbol Values
t
t
t
min.
15 +
10 +
15 +
15 +
– 10 +
–
–
40 +
65 +
A
C
F
Max. CPU Clock
t
t
t
t
t
t
A
A
A
A
C
C
= 20 MHz
t
A
46
TCL
2TCL
2TCL
max.
–
–
–
–
–
5
30
–
–
<ALECTL>
(15 – <MCTC>)
(1 – <MTTC>)
min.
TCL – 10 +
TCL – 15 +
TCL – 10 +
TCL – 10 +
– 10 +
–
–
2TCL – 10
+
3TCL – 10
+
t
t
C
C
1/2TCL = 1 to 20 MHz
Variable CPU Clock
t
A
t
t
t
t
A
A
A
A
max.
–
–
–
–
–
5
TCL + 5
–
–
C167SR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns