SAB-C509-LM SIEMENS [Siemens Semiconductor Group], SAB-C509-LM Datasheet - Page 63

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SAB-C509-LM

Manufacturer Part Number
SAB-C509-LM
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
Power Saving Modes
The C509-L provides three power saving modes in which power consumption can be significantly
reduced.
Table 14 gives a general overview of the entry and exit procedures of the power saving modes.
Table 14
Power Saving Modes Overview
Mode
Idle mode
Software
Power-Down Mode
Hardware
Power-Down Mode
Slow Down Mode
In the power down mode of operation,
be ensured, however, that
is restored to its normal operating level, before the power down mode is terminated.
If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals)
remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is
disturbed and replaced by the reset state of the C509-L.
Semiconductor Group
– Idle mode
– Power down mode
– Slow-down mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work.
The operation of the C509-L is completely stopped and the oscillator is turned off. This mode
is used to save the contents of the internal RAM with a very low standby current. Power down
mode can be entered by software or by hardware (pin HWPD).
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by eight. This slows down all parts of the controller, the CPU and all
peripherals, to 1/8 th of their normal operating frequency. Slowing down the frequency greatly
reduces power consumption.
Entering
2-Instruction
Example
ORL PCON, #01H
ORL PCON, #20H
ORL PCON, #02H
ORL PCON, #40H
Low level at pin
HWPD
ORL PCON,#10H
V
CC
is not reduced before the power down mode is invoked, and that
V
CC
can be reduced to minimize power consumption. It must
Leaving by
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
Hardware Reset
High level at pin
HWPD
ANL PCON,#0EFH
or
Hardware Reset
62
Remarks
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Oscillator frequency is
reduced to 1/8 of its nominal
frequency
C509-L
V
CC

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