ISL6255 INTERSIL [Intersil Corporation], ISL6255 Datasheet - Page 19

• Manufacturer Part Number: ISL6255
• Description: Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers
• Manufacturer: INTERSIL [Intersil Corporation]

where
Compensator design goal:
• High DC gain
• Loop bandwidth f
• Gain margin: >10dB
• Phase margin: 40°
The compensator design procedure is as follows:
The loop gain T
gain. Therefore, the compensator resistance R
determined by:
where g
amplifier. Compensator capacitor C1 is then given by:
Example: V
C
V
R
compensator capacitor C
voltage loop compensator: R
C
R
A
1. Put compensator zero at
2. Put one compensator pole at zero frequency to achieve
1
1
o
PWM
1
v
=10 µ F/10m Ω , L=10 µ H, g
=10k Ω . Put the compensator zero at 1.5kHz. The
( )
=
=
S
ω
high DC gain, and put another compensator pole at either
esr zero frequency or half switching frequency, whichever
is lower.
R
2
cz
=
π
1
=V
ω
1
ω
FIGURE 18. VOLTAGE LOOP COMPENSATOR
m
v ˆ
f
g
=
cz
c
v ˆ
IN
comp
m
cz
V
(
is the trans-conductance of the voltage loop error
FB
1 −
o
V
=
/11, f
in
C
FB
=20V, V
R
o
3
1
R
=
1
C
)
v
T
c
g
R
1
(S) at cross over frequency of f
=25kHz, then compensator resistance
m
o
,
1
C
c
Vo
Vo
Vo
Vo
1
:
o
o
SC
V
V
+
V
V
=16.8V, I



REF
REF
FB
FB
ω
1
5
1
S
cz
1
−
is C
20
-
-
-
-
+
+
+
+
1
m
1
19
g
g
=250 µ s, R



=10K, C
m
m
1
f
o
s
=9.2nF. Therefore, choose
=2.6A, f
C1
C1
R1
R1
V
V
1
COMP
COMP
=10nF.
T
s
=300kHz,
=0.2 Ω , V
1
c
is
has unity
FB
ISL6255, ISL6255A
=2.1V,
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
GND and VDD Pin
At least one high quality ceramic decoupling cap should be
used to cross these two pins. The decoupling cap can be put
close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
PGND Pin
PGND pin should be laid out to the negative side of the
relevant output cap with separate traces.The negative side
of the output capacitor must be close to the source node of
the bottom MOSFET. This trace is the return path of LGATE.
1. Top Layer: signal lines, or half board for signal lines and
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
the other half board for power lines
Power traces
June 17, 2005
FN9203.1