ISL6315 INTERSIL [Intersil Corporation], ISL6315 Datasheet - Page 14

• Manufacturer Part Number: ISL6315
• Description: Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers
• Manufacturer: INTERSIL [Intersil Corporation]

and E represents the total output capacitance and its
equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6315) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 8. Use the following guidelines for locating the
poles and zeros of the compensation network:
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
F
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
4. Calculate R3 such that F
2. Calculate C1 such that F
3. Calculate C2 such that F
LC
value for R2 for desired converter bandwidth (F
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost).
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
=
R2
C2
R3
C3
C1
---------------------------
2π
=
=
=
=
=
⋅
1
--------------------- -
F
----------- - 1
-------------------------------------------------
2π R3 0.7 F
-------------------------------------------- -
d
---------------------------------------------------------
2π R2 C1 F
----------------------------------------------- -
2π R2 0.5 F
F
SW
L C
V
MAX
SW
0
LC
OSC
R1
⋅
; typically 0.1 to 0.3 of F
⋅
⋅
⋅
P2
). F
–
⋅
⋅
V
is placed below F
⋅
⋅
SW
⋅
1
1
R1 F
IN
C1
LC
⋅
represents the per-channel switching
⋅
⋅
⋅
F
⋅
LC
(to adjust, change the 0.5 factor to
0
SW
CE
LC
F
Z1
P1
CE
–
Z2
14
1
is placed at a fraction of the F
=
is placed at F
is placed at F
----------------------- -
2π C E
0dB
SW
CE
⋅
SW
1
/F
(typically, 0.5 to 1.0
and 180°. The
⋅
) and adequate phase
LC
, the lower the F
P2
CE
LC
. Calculate C3
lower in
.
0
).
LC
Z1
ISL6315
ISL6315
,
frequency response of the modulator (G
compensation (G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 9 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log-log graph of Figure 9 by adding the modulator gain, G
(in dB), to the feedback compensation gain, G
is equivalent to multiplying the modulator transfer function and
the compensation transfer function and then plotting the
resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
G
G
G
F
F
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Z1
Z2
MOD
FB
CL
0
f ( )
f ( )
=
=
LOG
f ( )
------------------------------- -
2π R2 C1
-------------------------------------------------- -
2π
20
=
=
⋅
log
=
G
----------------------------------------------------- - ⋅
s f ( ) R1
---------------------------------------------------------------------------------------------------------------------------- -
(
⋅
⋅
1
(
1
MOD
d
----------------------------- -
R1
1
+


MAX
+
R2
------- -
R1
⋅
s f ( ) R3 C3
V
⋅
s f ( ) R2 C1
+
1
OSC


f ( ) G
R3
FB
⋅
⋅
⋅
V
⋅
⋅
(
F
) C3
C1
) and closed-loop response (G
IN
1
Z1
⋅
FB
F
+
⋅
F
⋅
LC
⋅
+
P2
s f ( )
Z2
----------------------------------------------------------------------------------------
1
f ( )
C2
+
F
)
against the capabilities of the error
P1
s f ( )
⋅
⋅
)
(


F
F
R1
1
CE
P1
=
⋅
+
F
(
---------------------------------------------- -
2π R2
P2
1
+
s f ( ) R2
E
CL
F
+
R3
+
0
⋅
=
s f ( ) E C
F
, is constructed on the
D
⋅
20
where s f ( )
P2
) C3
) C
------------------------------- -
2π R3 C3
⋅
log
⋅
⋅
G
⋅
1
--------------------- -
C1
MOD
⋅
⋅
C1 C2
CL
COMPENSATION GAIN
d
---------------------------------
OPEN LOOP E/A GAIN


+
⋅
--------------------- -
C1
1
CLOSED LOOP GAIN
MAX V
G
,
C1 C2
s
+
V OSC
⋅
MODULATOR GAIN
MOD
2
⋅
), feedback
C2
FB
f ( ) L C
+
FREQUENCY
⋅
⋅
C2
=
February 10, 2006
⋅
(in dB). This
IN


2π f j
CL


⋅
G
⋅ ⋅
):
FB
FN9222.0
MOD