ISL6322 INTERSIL [Intersil Corporation], ISL6322 Datasheet - Page 32

• Manufacturer Part Number: ISL6322
• Description: Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P
UPPER MOSFET POWER CALCULATION
In addition to r
upper-MOSFET losses are due to currents conducted
across the input voltage (V
substantially higher portion of the upper-MOSFET losses are
dependent on switching frequency, the power calculation is
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode
reverse-recovery charge, Q
r
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 25,
the required time for this commutation is t
approximated associated power loss is P
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET
reverse-recovery charge, Q
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P
P LOW 2
P
P
P
DS(ON)
UP 1 ,
UP 2 ,
UP 3 ,
,
≈
≈
=
V
V
=
conduction loss.
V
IN
IN
IN
V D ON
S
⋅
⋅
⎛
⎝
(
⋅
, and the length of dead times, t
⎛
⎜
⎝
I
----- -
Q
N
I
----- -
M
N
DS(ON)
M
rr
+
) f S
–
⋅
⋅
I
-------- -
I
-------- -
PP
f
PP
2
2
S
⋅
⎞
⎠
⎞
⎟
⎠
losses, a large portion of the
⋅
⎛
⎜
⎝
⋅
I
------
⎛
⎜
⎝
⎛
⎜
⎝
N
M
t
----
t
----
2
2
M
1
2
+
⎞
⎟
⎠
IN
⎞
⎟
⎠
, V
I PP
--------- -
rr
rr
⋅
UP,2
⋅
2
) during switching. Since a
, and the upper MOSFET
. Since the inductor current has
32
f
f
2
D(ON)
S
S
⎞
⎟
⎠
. In Equation 26, the
⋅
UP,3
.
t
d1
, the switching
+
.
⎛
⎜
⎜
⎝
I
------
LOW,1
N
M
UP,1
1
–
I
--------- -
and the
PP
2
d1
.
⎞
⎟
⎟
⎠
and P
⋅
and t
rr
t
, it is
d2
LOW,2
d2
(EQ. 24)
(EQ. 25)
(EQ. 26)
(EQ. 27)
, at
.
ISL6322
Finally, the resistive part of the upper MOSFET is given in
Equation 28 as P
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 25, 26, 27 and 28. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See Layout Considerations paragraph
for thermal transfer improvement suggestions.
When designing the ISL6322 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 29
and 30, respectively.
In Equations 29 and 30, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
P
P
P
P
I
Qg_TOT
UP 4 ,
DR
Qg_TOT
Qg_Q2
Qg_Q1
=
≈
r
⎛
⎝
DS ON
3
-- - Q
2
, due to the gate charge of MOSFETs and the
=
=
=
⋅
(
Q
3
-- - Q
2
P
G1
G2
⋅
Qg_Q1
)
⋅
⋅
G1
⋅
N
PVCC F
UP,4
Qg_Q2
⎛
⎜
⎝
Q1
I
----- -
N
⋅
M
+
PVCC F
⎞
⎟
⎠
.
+
P
2
Q
Qg_Q2
⋅
⋅
G1
d
is the total lower gate drive power
G2
Qg_Q1
+
SW
⋅
and Q
I
--------- -
⋅
PP
12
N
SW
⋅
+
2
Q2
N
I
Q
Q2
⋅
⎞ N
⎠
is the total upper gate drive
N
G2
⋅
⋅
VCC
Q1
⋅
N
) is defined at the
PHASE
Q
PHASE
⋅
N
is the driver total
PHASE
⋅
F
SW
August 21, 2006
+
I
Q
(EQ. 30)
(EQ. 29)
(EQ. 28)
FN6328.0