ISL6322_07 INTERSIL [Intersil Corporation], ISL6322_07 Datasheet

ISL6322_07

Manufacturer Part Number

ISL6322_07

Description

Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications

Manufacturer

INTERSIL [Intersil Corporation]

Datasheet

1.ISL6322_07.pdf (41 pages)

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Four-Phase Buck PWM Controller with

Integrated MOSFET Drivers and I

Interface for Intel VR10, VR11, and AMD

Applications

The ISL6322 four-phase PWM control IC provides a

precision voltage regulation system for advanced

microprocessors. The integration of power MOSFET drivers

into the controller IC marks a departure from the separate

PWM controller and driver configuration of previous

multiphase product families. By reducing the number of

external parts, this integration is optimized for a cost and

space saving power management solution.

One outstanding feature of this controller IC is its

multi-processor compatibility, allowing it to work with both Intel

and AMD microprocessors. Included are programmable VID

codes for Intel VR10, VR11, as well as AMD DAC tables. A

unity gain, differential amplifier is provided for remote voltage

sensing, compensating for any potential difference between

remote and local grounds. The output voltage can also be

positively or negatively offset through the use of a single

external resistor.

The ISL6322 includes an I

controller to communicate with other devices over an I

bus. Signals sent over this bus can command the ISL6322 to

adjust voltage margining offset, converter switching

frequency, and overvoltage protection levels, and can select

the integrated driver adaptive dead time scheme.

The ISL6322 also includes advanced control loop features

for optimal transient response to load apply and removal.

One of these features is highly accurate, fully differential,

continuous DCR current sensing for load line programming

and channel current balance. Active Pulse Positioning (APP)

modulation is another unique feature, allowing for quicker

initial response to high di/dt load transients.

This controller also allows the user the flexibility to choose

between PHASE detect or LGATE detect adaptive dead time

schemes. This ability allows the ISL6322 to be used in a

multitude of applications where either scheme is required.

Protection features of this controller IC include a set of

sophisticated overvoltage, undervoltage, and overcurrent

protection. Furthermore, the ISL6322 includes protection

against an open circuit on the remote sensing inputs.

Combined, these features provide advanced protection for the

microprocessor and power system.

C interface, allowing the

Data Sheet

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Features

• Integrated Multiphase Power Conversion

• Precision Core Voltage Regulation

• Optimal Transient Response

• Fully Differential, Continuous DCR Current Sensing

• I

• User Selectable I

• User Selectable Adaptive Dead Time Scheme

• Variable Gate Drive Bias: 5V to 12V

• Multi-Processor Compatible

• Microprocessor Voltage Identification Inputs

• Overcurrent Protection

• Multi-Tiered Overvoltage Protection

• Digital Soft-Start

• Selectable Operation Frequency up to 1.5MHz Per Phase

• Pb-Free Plus Anneal Available (RoHS Compliant)

- 2-Phase or 3-Phase Operation with Internal Drivers

- 4-Phase Operation with External PWM Driver Signal

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over Temperature

- Adjustable Reference-Voltage Offset

- Active Pulse Positioning (APP) Modulation

- Adaptive Phase Alignment (APA)

- Accurate Load Line Programming

- Precision Channel Current Balancing

- Voltage Margining Offset

- Switching Frequency Adjustment

- Overvoltage Protection Level Adjustment

- Selects Adaptive Dead Time Scheme

1000_110x or 1000_111x

- PHASE Detect or LGATE Detect for Application

- Intel VR10 and VR11 Modes of Operation

- AMD Mode of Operation

- 8-bit DAC

- Selectable between Intel’s Extended VR10, VR11, AMD

- Dynamic VID Technology

February 15, 2007

C Interface

Flexibility

5-bit, and AMD 6-bit DAC Tables

All other trademarks mentioned are the property of their respective owners.

Intersil (and design) is a registered trademark of Intersil Americas Inc.

C “Slave Only” Device Address:

ISL6322

FN6328.1

Related parts for ISL6322_07

ISL6322_07 Summary of contents

Page 1

Data Sheet Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I Interface for Intel VR10, VR11, and AMD Applications The ISL6322 four-phase PWM control IC provides a precision voltage regulation system for advanced microprocessors. The integration of power ...

Page 2

Ordering Information PART NUMBER PART TEMP. (Note) MARKING (°C) ISL6322CRZ* ISL6322 CRZ 7x7 QFN ISL6322IRZ* ISL6322 IRZ - 7x7 QFN *Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus ...

Page 3

Block Diagram OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC SS/RST/ SCL LOGIC SDA MODE/DAC VRSEL SELECT VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 REF FB COMP ...

Page 4

ISL6322 Integrated Driver Block Diagram DRSEL PWM SOFT-START AND FAULT LOGIC 2 Simplified I C Bus Architecture SCL SDA SCL SLAVE SLAVE ISL6322 ISL6322 SHOOT- GATE CONTROL THROUGH LOGIC PROTECTION SDA BUS ...

Page 5

Typical Application - ISL6322 (4-Phase) FB IDROOP VDIFF COMP VSEN RGND +5V VCC OFS FS REF SCL SDA SS / RST / A0 ISL6322 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PGOOD +12V EN GND 5 ISL6322 ISL6322 ...

Page 6

Typical Application - ISL6322 with NTC Thermal Compensation (4-Phase) FB IDROOP COMP VSEN RGND +5V VCC OFS FS REF SCL SDA SS / RST / A0 ISL6322 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PGOOD +12V EN GND ...

Page 7

Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Supply Voltage, PVCC . ...

Page 8

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued) PARAMETER REFERENCE AND DAC System Accuracy (1.000V to 1.600V) System Accuracy (0.600V to 1.000V) System Accuracy (0.375V - 0.600V) DAC Input Low Voltage (VR10, VR11) DAC Input High Voltage (VR10, VR11) ...

Page 9

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued) PARAMETER Overvoltage Hysteresis SWITCHING TIME (Note 3) UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-On Non-Overlap LGATE Turn-On Non-Overlap GATE DRIVE RESISTANCE (Note 3) Upper ...

Page 10

Functional Pin Description VCC VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1μF ceramic capacitor. PVCC1_2 and PVCC3 These pins are the power supply pins for ...

Page 11

PHASE1, PHASE2, and PHASE3 Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path for the upper MOSFET drives. LGATE1, LGATE2, and LGATE3 These pins are used to control the lower MOSFETs. Connect ...

Page 12

PWM pulse of the previous phase. The peak-to-peak current for each phase is about 7A, and the DC components of the inductor currents combine to feed the load. To understand the ...

Page 13

Channel-Current Balance One important benefit of multiphase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer avoids the complexity of driving parallel MOSFETs and the expense of ...

Page 14

L ------------- + 1 ⎝ ⎠ DCR ⋅ ⋅ ------------------------------------------------------- - K DCR ⋅ ) ⎛ ⎞ ⋅ ⋅ ⎜ ⎟ s ----------------------- - ...

Page 15

TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 VID0 VID5 ...

Page 16

TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 VID0 VID5 ...

Page 17

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...

Page 18

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...

Page 19

TABLE 4. AMD 5-BIT VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 ...

Page 20

Voltage Regulation The integrating compensation network shown in Figure 6 insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current ...

Page 21

Output-Voltage Offset Programming The ISL6322 allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R is connected between OFS OFS and VCC, the voltage across it is regulated to ...

Page 22

AMD Dynamic VID Transitions When running in AMD 5-bit or 6-bit modes of operation, the ISL6322 responds differently to a dynamic VID change than when in Intel VR10 or VR11 mode. In the AMD modes, the ISL6322 still checks the ...

Page 23

MOSFETs. The ΔV BOOT_CAP allowable droop in the rail of the upper gate drive. 1.6 1.4 1.2 1. 0.8 0 100nC GATE 0.4 50nC 0.2 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 ΔV BOOT_CAP FIGURE 9. ...

Page 24

AMD soft-start sequence. For the Intel VR10 and VR11 modes of operation, the soft-start sequence is composed of four periods, as shown in Figure 11. Once the ISL6322 is released from shutdown and soft-start ...

Page 25

OUTPUT PRECHARGED ABOVE DAC LEVEL OUTPUT PRECHARGED BELOW DAC LEVEL GND> GND> FIGURE 13. SOFT-START WAVEFORMS FOR ISL6322-BASED MULTIPHASE CONVERTER Pre-Biased Soft-Start The ISL6322 also has the ability to start up into a pre-charged output, without causing ...

Page 26

The LGATE outputs remain high and PWM4 remains low until VDIFF falls 100mV below the OVP threshold that tripped the overvoltage protection circuitry. The ISL6322 will continue to protect the load ...

Page 27

OUTPUT CURRENT, 50A/DIV 0A OUTPUT VOLTAGE, 500mV/DIV 0V 3ms/DIV FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE Individual Channel Overcurrent Limiting The ISL6322 has the ability to limit the current in each individual channel without shutting down the entire regulator. This ...

Page 28

Acknowledge Each address and data transmission uses 9 clock pulses. The ninth pulse is the acknowledge bit (A). After the start condition, the master sends 7 slave address bits and a R/W bit during the next 8 clock pulses. During ...

Page 29

I C Read and Write Protocol Write to a Single Register S slave_addr + W A reg_addr Write to Both Registers S slave_addr + W A 0000_0000 Read from a Single Register S slave_addr + W A reg_addr Read ...

Page 30

TABLE 8. REGISTER RGS1 (VOLTAGE MARGINING OFFSET) (Continued) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 X X VO5 VO4 VO3 VO2 ...

Page 31

TABLE 9. REGISTER RGS2 (ADAPTIVE DEADTIME CONTROL/OVERVOLTAGE PROTECTION/SWITCHING FREQUENCY) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 X X DT1 DT0 OVP ...

Page 32

An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage ...

Page 33

PVCC BOOT R G HI1 UGATE R R LO1 G1 PHASE FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH PVCC HI2 LGATE LO2 G2 FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH The total gate drive ...

Page 34

Plug the inductor L and DCR component values, and the value for C chosen in step 1, into Equation calculate the value for ------------------------- OCP ⋅ 1 DCR C ...

Page 35

Load-line Regulation” on page 35 and “Compensation without Load-line Regulation” on page 36. COMPENSATION WITH LOAD-LINE REGULATION The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the ...

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