AT89S8253-24PSC ATMEL [ATMEL Corporation], AT89S8253-24PSC Datasheet
AT89S8253-24PSC
Related parts for AT89S8253-24PSC
AT89S8253-24PSC Summary of contents
Page 1
... The on-chip downloadable Flash allows the program mem- ory to be reprogrammed in-system through an SPI serial interface conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with downloadable Flash on a monolithic chip, the Atmel AT89S8253 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. ...
Page 2
... Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector, four-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8253 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes ...
Page 3
... P1.1 (T2EX) (WR) P3 P1.0 (T2) (RD) P3 VDD XTAL2 10 33 PWRVDD XTAL1 11 32 P0.0 (AD0) GND 12 31 P0.1 (AD1) PWRGND 13 30 P0.2 (AD2) (A8) P2 P0.3 (AD3) (A9) P2 P0.4 (AD4) (A10) P2 P0.5 (AD5) (A11) P2 P0.6 (AD6) (A12) P2 P0.7 (AD7) (A13) P2 EA/VPP (A14) P2 ALE/PROG (A15) P2 PSEN AT89S8253 3 ...
Page 4
... Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. AT89S8253 4 ,150 A typical) because of the weak internal pull-ups. µ ...
Page 5
... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S8253, as shown in the following table. Port Pin P3 ...
Page 6
... Input to the inverting oscillator amplifier and input to the internal clock operating circuit. 3.15 XTAL2 Output from the inverting oscillator amplifier. 4. Block Diagram PSEN ALE/PROG RST AT89S8253 6 for internal program executions. This pin also receives the 12-volt CC ) during Flash programming when 12-volt programming is PP P0 ...
Page 7
... User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Table 5-1. AT89S8253 SFR Map and Reset Values 0F8H B 0F0H 00000000 ...
Page 8
... IP and IPH registers. IPH bits have the same functions as IP bits, except IPH has higher priority than IP. By using IPH in conjunction with IP, a priority level may be set for each interrupt. AT89S8253 8 – ...
Page 9
... It can be set and reset under software control and is not affected by RESET. 6. Data Memory – EEPROM and RAM The AT89S8253 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. ...
Page 10
... WRTINH (Write Inhibit READ-ONLY bit which is cleared by hardware when V WRTINH of the on-chip EEPROM to be executed. When this bit is cleared, an ongoing programming cycle will be aborted or a new programming cycle will not start. Figure 6-1. Data EEPROM Write Sequence EEMEN EEMWE EELD MOVX DATA RDY/BSY AT89S8253 10 EELD EEMWE EEMEN ...
Page 11
... Brown-out Reset The AT89S8253 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level of 2.4V (max). The trigger level for the BOD is nominally 2.2V. The purpose of the BOD is to ensure that if V cuting at speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution ...
Page 12
... The WDT is disabled by Power-on Reset and during Power-down mode. When WDT times out without being serviced or disabled, an internal RST pulse is generated to reset the CPU. See Table 8-1 Table 8-1. AT89S8253 12 for the WDT period selections. Watchdog Timer Time-out Period Selection WDT Prescaler Bits ...
Page 13
... If HWDT = 1, this bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). Figure 8-1. Software Mode – Watchdog Timer Sequence WDTEN WSWRST 3286L–MICRO–8/08 PS0 WDIDLE DISRTO Writes AT89S8253 Table 8-2). Reset Value = 0000 0000B HWDT WSWRST WDTEN 0 13 ...
Page 14
... Timer 0 and 1 Timer 0 and Timer 1 in the AT89S8253 operate the same way as Timer 0 and Timer 1 in the AT89S51 and AT89S52. For more detailed information on the Timer/Counter operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 10. Timer 2 Timer 16-bit Timer/Counter that can operate as either a timer or an event counter. The ...
Page 15
... RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus- trated in 3286L–MICRO–8/08 RCLK TCLK EXEN2 Figure 10-1. AT89S8253 Reset Value = 0000 0000B TR2 C/T2 CP/RL2 Table 10-2) and T2MOD (see 15 ...
Page 16
... T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. AT89S8253 16 C/ TH2 ...
Page 17
... The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. Figure 10-2. Timer 2 in Auto Reload Mode (DCEN = 0) Figure 10-3. Timer 2 Auto Reload Mode (DCEN = 1 Timer 2 Auto Reload Mode (DCEN = 1) 3286L–MICRO–8/08 AT89S8253 17 ...
Page 18
... Normally timer, it increments every machine cycle (at 1/12 the oscillator frequency baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below. where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. AT89S8253 18 C/ TH2 TL2 ...
Page 19
... Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. Figure 12-1. Timer 2 in Clock-out Mode 3286L–MICRO–8/08 Figure 10-4. This figure is valid only if RCLK or Oscillator Frequency Clock Out Frequency = ------------------------------------------------------------------------------------------ - × 65536 – AT89S8253 Figure 12-1. This ( ) ] RCAP2H,RCAP2L 19 ...
Page 20
... UART The UART in the AT89S8253 operates the same way as the UART in the AT89S51 and AT89S52. For more detailed information on the UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 13.1 Enhanced UART In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition ...
Page 21
... UART drivers which do not make use of this feature. 3286L–MICRO–8/08 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX AT89S8253 21 ...
Page 22
... Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the RI other modes, in any serial reception (except see SM2). Must be cleared by software. Notes: 1. SMOD0 is located at PCON.6. AT89S8253 22 – POF GF1 5 ...
Page 23
... Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89S8253 and peripheral devices or between multiple AT89S8253 devices. The AT89S8253 SPI features include the following: • Full-Duplex, 3-Wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 24
... WCOL, and continues trans- mission without stopping and restarting the clock generator. As long as the CPU can keep the write buffer full in this manner, multiple bytes may be transferred with minimal latency between bytes. AT89S8253 24 OSCILLATOR MSB DIVIDER ÷ ...
Page 25
... Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE. 2. Enable the master SPI prior to the slave device. 3. Slave echoes master on next Tx if not loaded with new data. 3286L–MICRO–8/08 DORD MSTR CPOL AT89S8253 Reset Value = 0000 0100B CPHA SPR1 SPR0 follows: OSC. ...
Page 26
... When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the SPDR register. Table 14-3. SPDR – SPI Data Register SPDR Address = 86H Not Bit Addressable SPD7 SPD6 Bit 7 6 AT89S8253 26 LDEN – – SPD5 SPD4 SPD3 ...
Page 27
... Serial Clock Cycle Time Clock High Time Clock Low Time Rise Time Fall Time Serial Input Setup Time Serial Input Hold Time Serial Output Hold Time Serial Output Valid Time AT89S8253 Serial Slave 2 MUX Serial Out LATCH CLK Parallel Slave ...
Page 28
... SOX t SSE t SSD Figure 14-4. SPI Master Timing (CPHA = 0) (CPOL = 0) (CPOL = 1) MISO MOSI AT89S8253 28 SPI Slave Characteristics Parameter Oscillator Period Serial Clock Cycle Time Clock High Time Clock Low Time Rise Time Fall Time Serial Input Setup Time Serial Input Hold Time ...
Page 29
... Figure 14-7. SPI Slave Timing (CPHA = 1) (CPOL = 0) (CPOL = 1) 3286L–MICRO–8/ SCK SSE t SHSL SCK SCK t SLSH t SOE SS SCK SCK MISO MOSI SS SCK SCK MISO MOSI AT89S8253 SLSH t SHSL t t SOV SOH t SIS SOV t SSD t SOX t SIH ...
Page 30
... Note: *Not defined but normally LSB of previously transmitted character 15. Interrupts The AT89S8253 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE ...
Page 31
... User software should never write 1s to reserved bits, because they may be used in future AT89 products. 3286L–MICRO–8/08 Source RST or POR or BOD IE0 TF0 IE1 TF1 SPIF ET2 ES ET1 AT89S8253 Vector Address 0000H 0003H 000BH 0013H 001BH 0023H Reset Value = 0X00 0000B EX1 ET0 EX0 ...
Page 32
... PT2H Timer 2 Interrupt Priority High PSH Serial Port Interrupt Priority High PT1H Timer 1 Interrupt Priority High PX1H External Interrupt 1 Priority High PT0H Timer 0 Interrupt Priority High PX0H External Interrupt 0 Priority High Figure 15-1. Interrupt Sources AT89S8253 32 PT2 PS PT1 PT2H PSH PT1H 5 4 ...
Page 33
... Figures 16-2 and 16-3 C1 ± for Crystals = 5 pF ± for Ceramic Resonators Quartz Crystal Clock Input 6.5 6 5.5 5 4.5 4 3.5 3 2 Frequency (MHz) AT89S8253 Figure 16-1. Either a quartz crystal or illustrate the relationship between sam ...
Page 34
... To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. Table 17-1. Mode Idle Idle Power-down Power-down AT89S8253 34 Ceramic Resonator Clock Input ...
Page 35
... Exit from power-down mode. 19. Program Memory Lock Bits The AT89S8253 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. ...
Page 36
... The code and data memory arrays in the AT89S8253 are programmed byte-by-byte or by page in either programming mode. To reprogram any non-blank byte in the parallel or serial mode, the user needs to invoke the Chip Erase operation first to erase both arrays since there is no built-in auto-erase capability ...
Page 37
... Set RST and EA pins to “L”. e. Turn V Data Polling: The AT89S8253 features DATA Polling to indicate the end of any programming cycle. During a write cycle in the parallel or serial programming mode, an attempted read of the last loaded byte will result in the complement of the written datum on P0.7 (parallel mode), and on the MSB of the serial output byte on MISO (serial mode) ...
Page 38
... XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 24 MHz oscillator clock, the maximum SCK frequency is 1.5 MHz. 23. Serial Programming Algorithm To program and verify the AT89S8253 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: a. Apply power between VCC and GND pins. ...
Page 39
... Byte 0 ... Byte 63 xxxx xxxx Byte 0 ... Byte 63 xx AT89S8253 Table 24-1. Byte n Operation Enable Serial Programming while RST is high Chip Erase both the 12K and 2K memory arrays Write data to Program Memory – Byte Mode Read data from Program Memory – ...
Page 40
... Fuse2 (x2 Mode Selection Fuse): This fuse enables/disables the internal x2 clock mode. Fuse3 (User Row Access Fuse): This fuse enables/disables writing to the programmable user row. Fuse4 (Clock Selection Fuse): This fuse selects between an external clock source and a quartz crystal as the clock input. AT89S8253 40 ALE ...
Page 41
... AT89S8253 AT89S8253 ADDR 0000H/37FFH P2 A13 P3.3 ALE P3.4 P3.5 P3.6 P3.7 EA P3.0 3-24 MHz XTAL1 RST EXTERNAL CLOCK GND PSEN Oscillator Bypass Fuse (Fuse4) On AT89S8253 ADDR 0000H/37FFH P0 P2 A13 P3.3 ALE P3.4 P3.5 P3.6 P3.7 EA 3-24 MHz XTAL1 RST EXTERNAL CLOCK GND PSEN Oscillator Bypass Fuse (Fuse4 PGM ...
Page 42
... DATA OUTPUT P1.7/SCK CLOCK IN XTAL2 3-24 MHz XTAL1 GND Oscillator Bypass Fuse (Fuse4) Off AT89S8253 42 2. INSTRUCTION INPUT DATA OUTPUT CLOCK IN 3-24 MHz RST V EXTERNAL IH CLOCK 2.7V to 5.5V AT89S8253 V CC P1.5/MOSI P1.6/MISO P1.7/SCK XTAL1 RST V IH GND Oscillator Bypass Fuse (Fuse4) On 3286L–MICRO–8/08 ...
Page 43
... PROG Low to XTAL Halt PLX t XTAL Halt to RST Low XRL t RST Low to Power Off PWRDN Notes: 1. Power On occurs once Chip Erase. 3286L–MICRO–8/08 (1) (2) High PP Low PP reaches 2.4V. CC AT89S8253 Min Max 11.5 12.5 1 150 256 4 ...
Page 44
... Figure 26-1. Flash/EEPROM Programming and Verification Waveforms – Parallel Mode AT89S8253 44 3286L–MICRO–8/08 ...
Page 45
... MSB MSB Change Sample Outputs Inputs t OVSL t SHOX = -40⋅C to 85⋅ Min 3 41 CLCL 8 t CLCL t CLCL 2 t CLCL 10 AT89S8253 LSB LSB t t SLSH SHSL t SHIV = 2.7V - 5.5V (Unless Otherwise Noted) CC Typ Max 24 33 4.5 Units MHz ...
Page 46
... OL Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89S8253 46 *NOTICE: = -40°C to 85°C and V = 2.7 to 5.5V, unless otherwise noted A CC Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST mA ...
Page 47
... QVWH t Data Hold after WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH 3286L–MICRO–8/08 = -40°C to 85°C and V = 2.7 to 5.5V, unless otherwise noted AT89S8253 Variable Oscillator Min Max Units 0 24 MHz CLCL CLCL ...
Page 48
... External Program Memory Read Cycle 33. External Data Memory Read Cycle AT89S8253 48 3286L–MICRO–8/08 ...
Page 49
... External Clock Drive Waveforms 36. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL 3286L–MICRO–8/08 AT89S8253 V = 2.7V to 5.5V CC Min Max Units MHz ...
Page 50
... Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V AT89S8253 50 = 2.7V to 5.5V and Load Capacitance = 80 pF. CC (1) - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V ...
Page 51
... CLOCK SIGNAL XTAL1 RST (NC) XTAL2 CLOCK SIGNAL XTAL1 V SS Tests in Active and Idle Modes CHCL CHCX V RST (NC) XTAL2 XTAL1 VSS AT89S8253 CHCX t CLCH t CLCL ...
Page 52
... I (Active Mode) Measurements CC AT89S8253 52 AT89S8253 I Active @ 25 CC With Internal Clock Oscillator x1 Mode 4.00 3.50 3.00 2.50 2.00 1. Frequency (MHz) AT89S8253 I CC With Internal Clock Oscillator x1 Mode 4.00 3.50 3.00 2.50 2.00 1. Frequency (MHz Active @ 3286L–MICRO–8/08 3 ...
Page 53
... I (Idle Mode) Measurements CC 47. I (Power Down Mode) Measurements CC 3286L–MICRO–8/08 AT89S8253 I Idle vs. Frequency 25°C CC With Internal Clock Oscillator x1 Mode 3 2.5 2 1 Frequency (MHz) AT89S8253 I in Power-down CC 2.5 2 1 (V) CC AT89S8253 =5V ...
Page 54
... Ordering Information 48.1 Standard Package Speed Power (MHz) Supply Ordering Code AT89S8253-24AC AT89S8253-24JC 2.7V to 5.5V AT89S8253-24PC AT89S8253-24PSC 24 AT89S8253-24AI AT89S8253-24JI 2.7V to 5.5V AT89S8253-24PI AT89S8253-24PSI 48.2 Green Package Option (Pb/Halide-free) Speed Power (MHz) Supply Ordering Code AT89S8253-24AU AT89S8253-24JU 24 2.7V to 5.5V AT89S8253-24PU AT89S8253-24PSU 44A 44-lead, Thin Plastic Gull Wing Quad Flat Package (TQFP) ...
Page 55
... Orchard Parkway San Jose, CA 95131 R 3286L–MICRO–8/08 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) AT89S8253 A2 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM SYMBOL A – – A1 0.05 – ...
Page 56
... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89S8253 56 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...
Page 57
... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 3286L–MICRO–8/08 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) AT89S8253 E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.381 – D 52.070 – ...
Page 58
... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-020, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89S8253 58 D PIN TITLE 42PS6, 42-lead (Shrink 0.070" ...
Page 59
Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...