ISL89160 INTERSIL [Intersil Corporation], ISL89160 Datasheet - Page 10

• Manufacturer Part Number: ISL89160
• Description: High Speed, Dual Channel, 6A, 4.5 to 16VOUT, Power MOSFET Driver
• Manufacturer: INTERSIL [Intersil Corporation]

Typical Application Circuit
This is an example of how the ISL89160, ISL89161,
ISL89162, MOSFET drivers can be applied in a zero
voltage switching full bridge. Two main signals are
required: a 50% duty cycle square wave (SQR) and a
PWM signal synchronized to the edges of the SQR input.
An ISL89162 is used to drive T1 with alternating half
cycles driving Q
Q
two high-side bridge FETs, the two low side bridge FETs
are turned on with a rising edge delay. The delay is setup
by the RCD network on the inputs to the ISL89160. The
duration of the delay is chosen to turn on the low-side
FETs when the voltage on their respective drains is at the
resonant valley. For a complete description of the ZVS
topology, refer to
Application Note”.
General PCB Layout Guidelines
The AC performance of the ISL89160, ISL89161,
ISL89162 depends significantly on the design of the PC
board. The following layout design guidelines are
recommended to achieve optimum performance:
• Place the driver as close as possible to the driven
• Understand where the switching power currents flow.
• Keep power loops as short as possible by paralleling
• Use planes where practical; they are usually more
• Avoid paralleling high amplitude di/dt traces with low
LL
power FET.
The high amplitude di/dt currents of the driven
power FET will induce significant voltage transients
on the associated traces.
the source and return traces.
effective than parallel traces.
level signal lines. High di/dt will induce currents and
consequently, noise voltages in the low level signal
lines.
PWM
V
V
V
V
SQR
V
and Q
V
LR
GUL
GLR
GLL
GUR
LL
LR
LL
LR
L
also with alternating half cycles. Unlike the
UL
AN1603
and Q
R
UR
10
“ISL6752_54 Evaluation Board
. An ISL89160 is used to drive
L
ISL89160, ISL89161, ISL89162
Red dashed lines
emphasize the
resonant
switching delay
of the low-side
bridge FETs
LL: lower left
LR: lower right
UL: upper left
UR: upper right
GLL: gate lower left
SQR
ZVS Full Bridge
U1A
U1B
ISL89162
LL
T1A
• When practical, minimize impedances in low level
• Be aware of magnetic fields emanating from
• If you must have traces close to magnetic devices,
• The use of low inductance components such as chip
• Use decoupling capacitors to reduce the influence of
• It may be necessary to add resistance to dampen
• Keep high dv/dt nodes away from low level circuits.
• Avoid having a signal ground plane under a high
• Do power dissipation and voltage drop calculations of
signal circuits. The noise, magnetically induced on a
10k resistor, is 10x larger than the noise on a 1k
resistor.
transformers and inductors. Gaps in these structures
are especially bad for emitting flux.
align the traces so that they are parallel to the flux
lines to minimize coupling.
resistors and chip capacitors is highly recommended.
parasitic inductance in the VDD and GND leads. To
be effective, these caps must also have the shortest
possible conduction paths. If vias are used, connect
several paralleled vias to reduce the inductance of
the vias.
resonating parasitic circuits especially on OUTA and
OUTB. If an external gate resistor is unacceptable,
then the layout must be improved to minimize lead
inductance.
Guard banding can be used to shunt away dv/dt
injected currents from sensitive circuits. This is
especially true for control circuits that source the
input signals to the ISL89163/164/165.
amplitude dv/dt circuit. This will inject di/dt currents
into the signal ground paths.
the power traces. Many PCB/CAD programs have
built in tools for calculation of trace resistance.
½ ISL89160
U2A
V
GUL
V
GLL
Q
LL
Q
UL
V
T2
bridge
Q
UR
Q
LR
½ ISL89160
V
V
GUR
GLR
U2B
November 2, 2010
T1B
FN7719.0
LR