AS1160 AMSCO [austriamicrosystems AG], AS1160 Datasheet
AS1160
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AS1160 Summary of contents
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... General Description The AS1160 (serializer) is designed to convert 10-bit wide parallel LVCMOS/LVTTL data bus signals into a single high-speed LVDS serial data stream with clock. ...
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... Absolute Maximum Ratings.................................................................................................................. 6 Electrical Characteristics ...................................................................................................................... Serializer Timing Requirements for TCLK ....................................................................................................... 6 Serializer Switching Characteristics ................................................................................................................ 6 Deserializer Electrical Characteristics ..............................................................................................................7 Deserializer Timing Requirements for REFCLK.............................................................................................. 8 Deserializer Switching Characteristics ............................................................................................................ 8 Scan Circuitry Timing Requirements............................................................................................................... 9 7 Typical Operating Characteristics AS1160 ......................................................................................... 8 Typical Operating Characteristics AS1161 9 Timing Diagrams ................................................................................................................................. 12 10 Detailed Description .......................................................................................................................... 19 Initialization .........................................................................................................................................................19 Data Transfer ...
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... SYNC1 and SYNC2 pins are combined through an OR gate. +3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital circuitry. DVDD Digital Circuit Ground. GND reference point for the digital part of the AS1160. DGND +3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD should be at the same potential and must not be more than 0 ...
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... TDI IEEE 1149.1 Test Data Output TDO TMS IEEE 1149.1 Test Mode Select Input IEEE 1149.1 Test Clock Input TCK TRSTN IEEE 1149.1 Test Reset Input No Connection. Leave open-circuit, do not connect these pins. N/C www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 N/C REFCLK AGND ROUT1 DGND ...
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... LVCMOS/LVTTL Output Bus LVDS Receiver Input/Output Bus LVDS Output Short-Circuit Duration Power Dissipation θ JA ESD Operating Temperature Storage Temperature Junction Temperature Package Body Temperature www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 may cause permanent damage to the device. These are stress ratings only, Min Max Units -0 ...
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... Serializer Switching Characteristics Table 6. Serializer Switching Characteristics Symbol Parameter Bus LVDS Low-to-High t LLHT Transition Time Bus LVDS High-to-Low t LHLT Transition Time www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 =28Ω 10pF, typical values @ T LOAD LOAD Conditions 3.6V IN Figure 34 on page 0V, DIN = High, PWDNN and DEN = V ...
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... Deserializer LVCMOS/LVTTL DC Specifications (input pins PWDNN, RCKR/FN, REN, REFCLK; output pins ROUT0:ROUT9, RCLK, LOCKN) V High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 1 Conditions Figure 21 on page 13 2 Figure 22 on page 14 Figure 23 on page 14 Figure 25 on page 15 Figure 24 on page 14 Figure 26 on page 20MHz ...
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... Room temperature, 3.3V DD Figure 27 on page 16 Room temperature, 3.3V R Data Valid OUT t Figure 28 on page 16 ROS Before RCLK Time R Data Valid After OUT t Figure 28 on page 16 ROH RCLK Time www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Conditions OUT PWDNN or REN = 0V OUT ...
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... TRSTN-to-TCK Recovery Time REC t TCK to TDO Delay D t TCK to TDO High Z Delay Z Note: All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 1 Pin/ Conditions Min Frequency OUTx ...
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... AS1160/AS1161 Datasheet - Typical Operating Characteristics AS1160 V = 3.6V 28Ω 10pF LOAD LOAD Figure 4. Supply Current vs Supply Voltage 90 f clk=20M clk=66M ...
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... Clock Frequency (MHz) Figure 14. Power-Down Current vs. Temperature 1000 900 800 700 600 500 -45 -30 - Temperature (°C) www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Figure 11. Power-Down Current vs Supply Voltage 1000 950 900 850 800 750 700 650 600 550 500 3.6 3.8 2.8 3 Figure 13. Supply Current vs Temperature ...
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... Figure 15. JTAG Timing Diagram TCK t REC TDI, TMS TDO t WR TRSTN Figure 16. Worst-Case Serializer ICC Test Pattern TCLK Odd D IN Even D IN Figure 17. Worst-Case Deserializer ICC Test Pattern RCLK Odd R OUT Even R OUT www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 t TCK SPW SPW Revision 1. ...
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... DO+ - DO- DIFF Figure 19. Deserializer CMOS/TTL Output Load and Transition Times CMOS/TTL Output Deserializer Figure 20. Serializer Input Clock Transition Time 90% TCLK 10% t CLKT Figure 21. Serializer Setup and Hold Times TCLK D IN0:9 www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 80% R LOAD V DIFF 28Ω 20% t LLHT 80% 20% 15pF t CLH 3V 90% ...
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... Figure 22. Serializer Tri-State Test Circuit and Timing DO+ R LOAD 28Ω DO- 10pF 10pF DEN Figure 23. Serializer Power Up Timing VDD PWDNN Figure 24. Serializer PLL Lock Time and PWDNN Tri-State Delays PWDNN TCLK DO+ DO- www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 3V DEN 1. HZD V OH DO+ t LZD DO tPWDL 2.0V <400 Cycles ...
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... SPW minimum timing met SYNC2 DO+ DO- SYNCPAT Figure 26. Serializer Delay D Symbol n D IN0:9 IN TCLK Start D Symbol OUT0:9 Bit DO DO- www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 t SPW Data SYNCPAT SYNCPAT D Symbol IN0:9 t TCP t SD Timing shown for TCKR/FN = high Stop Start D Symbol n OUT0:9 Bit Bit ...
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... Figure 28. Deserializer Data Valid Out Times RCKR/FN = Low RCKR/FN = High R OUT0:9 Figure 29. Deserializer Tri-State Test Circuit and Timing Diagram +7V LZ, ZL Open HZ, ZH Ω 500 OScope Ω 450 Ω 50 www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Stop Start Stop Start D Symbol IN0:9 Bit Bit Bit Bit ...
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... ZHLK LOCKN Tri-State R OUT0:9 Tri-State RCLK REN Figure 31. Deserializer PLL Lock Time from SYNCPAT PWDNN REFCLK RI+ RI- LOCKN R OUT0:9 Tri-State RCLK REN www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 t DSR1 SYNCPATs Data ZHR ZLR Tri-State SYNC Symbol or D RCKR/FN = low t RCLKL t DSR2 SYNCPATs Data ZHR ...
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... RNM Figure 34. Data Transfer Mode, V Diagram (V OD DIN0:9 TCLK www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 ) DJIT (DO+) - (DO-) Waveform Trigger Superimposed ICC Pattern RNM RNM Ideal Sampling Position = DO+ - DO-) OD AS1160 10 Parallel DO+ to Serial DO- Revision 1.01 0 Differential 1. 1.0V t DJIT R LOAD ...
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... When the deserializer detects edge transitions at the bus LVDS input, it will attempt to lock to the embedded clock information. When the deserializer locks to the bus LVDS clock, the LOCKN output will go low. When LOCKN is low, the deserializer outputs represent incoming bus LVDS data. www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 (see Figure 23 on page reaches V (2 ...
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... RCLK as the reference to data. The polarity of the RCLK edge is controlled by the RCKR/ OUT0 OUT9 FN input (see Figure 28 on page 16). R input gates (15pF load) with a 66MHz clock. www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 (see Figure 37 on page 24) ASIC R X 10-bit :R data is valid when LOCKN is low, otherwise R ...
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... When DEN is driven high, the serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWDNN, TCKR/FN). When pin REN is driven low, the deserializer enters tri-state. Consequently, the receiver output pins (R and RCLK will enter tri-state. The LOCKN output remains active, reflecting the state of the PLL. www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1. ...
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... Transmitting Data Once the serializer (AS1160) and deserializer (AS1161) are powered up, they must be phase locked to each other to transmit data. Phase locking occurs when the deserializer locks to incoming data or when the serializer sends patterns. The serializer sends SYNCPATs whenever the SYNC1 or SYNC2 inputs are high. The LOCKN output of the deserial- izer remains high until it has locked to the incoming data stream ...
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... As all BLVDS devices the AS1161 is hot pluggable but you have to follow some rules. Hot insertion should be performed with pins making contact in the following order: - Ground pins - V pins DD - I/O pins Note: When removing the device, the pin groups should be removed in reverse order from insertion. www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Parallel DO+ RI+ Output 56Ω -to- Latch ...
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... Transmission Media The transmission line characteristics affect the performance of the AS1160/AS1161. It’s recommended to use con- trolled-impedance media and to terminate at both ends of the transmission line should be used due to their superior signal quality and the less EMI generation. Noise which is picked up as common mode in the twisted pair is rejected by the differential receiver. It’ ...
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... It is the offset from t for the test mask within the eye opening. RNM DJIT The vertical limits of the mask are determined by the AS1161 receiver input threshold of ±75mV. www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 LOAD ...
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... BER (bit-error-rate) is better than 10 If both the AS1160 and the AS1161 have loaded the RUNBIST instruction into their instruction registers, both devices must move into the RTI state within 4K system clocks (at a SCLK of 66Mhz and TCK of 1MHz this allows for 66 TCK cycles) ...
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... AS1160/AS1161 Datasheet - Package Drawings and Markings The device is available in an CTBGA 49-bumps package. Figure 40. CTBGA 49-bumps Package www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1. ...
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... AS1161-BCTT Deserializer Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: For further information and requests, please contact us or find your local distributor at www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Table 14. Delivery Form Tape and Reel Tape and Reel http://www.austriamicrosystems.com/ICdirect mailto:sales@austriamicrosystems ...
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... No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1. ...