AD8197B-EVALZ AD [Analog Devices], AD8197B-EVALZ Datasheet - Page 13

• Manufacturer Part Number: AD8197B-EVALZ
• Description: 4:1 HDMI/DVI Switch with Equalization
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
INTRODUCTION
The AD8197B is a pin-to-pin HDMI 1.3 receive-compliant
replacement for the AD8197A. The primary function of the
AD8197B is to switch one of four (HDMI or DVI) single link
sources to one output. Each HDMI/DVI link consists of four
differential, high speed channels and four auxiliary single-
ended, low speed control signals. The high speed channels
include a data-word clock and three transition minimized differ-
ential signaling (TMDS) data channels running at 10× the data-
word clock frequency for data rates up to 2.25 Gbps. The four
low speed control signals are 5 V tolerant bidirectional lines
that can carry configuration signals, HDCP encryption, and
other information, depending upon the specific application.
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS
channels. Transmit and receive channel compensation is
provided for the high speed channels where the user can
(manually) select among a number of fixed settings.
The AD8197B has two control interfaces. Users have the option
of controlling the part through either the parallel control
interface or the I
parallel control interface is not able to control the switch status
of the input termination resistors and therefore has limited
usefulness in practical systems. Most systems use only the I
serial interface.
The AD8197B has eight user-programmable I
to allow multiple AD8197Bs to be controlled by a single I
A RESET pin is provided to restore the control registers of the
AD8197B to the parallel control interface and some default
values. In all cases, serial programming values override any
prior parallel programming values, and any use of the serial
control interface disables the parallel control interface until the
AD8197B is reset.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
VTTI power supply through a pair of single-ended 50 Ω on-
chip resistors, as shown in Figure 25. The input termination
status for each individual high speed differential (TMDS) input
pair can be controlled by programming the appropriate RX_TO
bit in the receiver settings register. Refer to Table 5 and Table 12.
By default, the input terminations are disabled (switched open)
after reset. The input terminations cannot be switched when
programming the AD8197B through the parallel control
interface. This limits the usefulness of the parallel control
interface.
Some systems require that the input terminations be switched
on only for the one selected HDMI source. The input termina-
tions for the three unselected HDMI sources require their input
termination switches to be open. The AD8197B can perform
2
C serial control interface. However, the
2
C slave addresses
2
C bus.
2
C
Rev. 0 | Page 13 of 28
this operation, but it is not automatic. To obtain this functionality,
the channel selection and the input termination status must be
separately programmed via the I
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually control the equalization level of the eight high
speed input channels by selectively programming the associated
RX_EQ bits in the receive equalizer register through the serial
control interface. Alternately, the user can globally control the
equalization level of all eight high speed input channels by
setting the PP_EQ pin of the parallel control interface. No
specific cable length is suggested for a particular equalization
setting because cable performance varies widely between
manufacturers; however, in general, the equalization of the
AD8197B can be set to 12 dB without degrading the signal
integrity, even for short input cables. At the 12 dB setting, the
AD8197B can equalize more than 20 meters of 24 AWG cable at
2.25 Gbps.
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two 50 Ω on-chip resistors
(see Figure 26). This termination is user-selectable; it can be
turned on or off by programming the TX_PTO bit of the
transmitter settings register through the serial control interface,
or by setting the PP_OTO pin of the parallel control interface.
The output termination resistors of the AD8197B back-
terminate the output TMDS transmission lines. These back-
terminations, as recommended in the HDMI 1.3 specification,
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8197B
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
The AD8197B output has a disable feature that places the
outputs in a tristate mode. This mode is enabled by program-
ming the HS_EN bit of the high speed device modes register
through the serial control interface or by setting the PP_EN pin
of the parallel control interface. Larger wire-OR’ e d arrays can be
constructed using the AD8197B in this mode.
IN_xx
IP_xx
Figure 25. High Speed Input Simplified Schematic
AVEE
VTTI
50Ω
2
C serial control interface.
50Ω
CABLE
EQ
AD8197B