ADUCM360 AD [Analog Devices], ADUCM360 Datasheet
ADUCM360
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ADUCM360 Summary of contents
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... Preliminary Technical Data FEATURES Analog Input/Output Dual (24-bit) ADCs (ADuCM360) Single (24-bit) ADC (ADuCM361) Single Ended and fully Differential inputs Programmable ADC output rate ( kHz) Simultaneous 50Hz/60Hz rejection 50SPS Continuous Conversion Mode 16.67SPS Single Conversion Mode Flexible input MUX for input channel selection to both ADCs ...
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... TEMP, SELECTABLE IOVDD/4 . VREF Sources . .. . AVDD/4 PRECISION REFERENCE BUF . BUF . VREF- VREF+ INT_REF GND_SW Figure 1. ADuCM360 Block Diagram Rev Page Preliminary Technical Data ON-CHIP POR 1.8V DIGITAL RESET LDO ON-CHIP XTAL0 OSC (3%) ARM XTAL1 16MHz CORTEX-M3 MCU 16MHz GPIO PORTs ...
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... Preliminary Technical Data TABLE OF CONTENTS Features ............................................................................................... 1 Functional Block Diagram ............................................................... 2 General Description .......................................................................... 4 Specifications ..................................................................................... 5 ADuCM360/ADuCM361 Microcontroller Electrical Specifications ................................................................................. 5 Noise Resolution of Primary and Auxiliary ADCs ................ Timing Diagrams ................................................................. 12 SPI Timing Diagrams ................................................................. 13 Absolute Maximum Ratings .......................................................... 16 ESD Caution ................................................................................ 16 Outline Dimensions ........................................................................ 21 Rev Page ADuCM360/ADuCM361 ...
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... ADuCM360/ADuCM361 GENERAL DESCRIPTION The ADuCM360 is a fully integrated, 4 kSPS, 24-bit data acqui- sition system incorporating dual, high performance multi- channel sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), 32-bit ARM Cortex M3® MCU, and Flash/EE memory on a single chip. The part is designed for direct interfacing to external precision sensors in both wired and battery powered applications ...
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... Preliminary Technical Data SPECIFICATIONS ADUCM360/ADUCM361 MICROCONTROLLER ELECTRICAL SPECIFICATIONS AVDD/IOVDD = 1 3.6V, Internal 1.2V reference, f noted. Table 1. ADuCM360/ADuCM361 Specifications Parameter Test Conditions/Comments ADC SPECIFICATIONS Conversion Rate 1 Chop off Chop on Both Primary & Auxiliary Channels No Missing Codes 1 Chop off (f Chop on (f RMS Noise and Data Output ...
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... ADuCM360/ADuCM361 Parameter Test Conditions/Comments Gain = 128 (AVDD >=2.0V) Common mode Voltage, Vcm 1 Vcm=(AIN(+)+AIN(-))/2, Gain=2 to 128 Input current will be higher when Vcm <0.5V Input Current 1,9 Gain = 1, Buffered mode (excluding pins with Vbias) Gain >1, Buffered mode (excluding pins with Vbias) Unbuffered mode. Input current ...
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... DAC0DAT register) Min AGND − AGND − kΩ 100 range (reference = 1 0.008 Rev Page ADuCM360/ADuCM361 Typ Max Unit AVDD-0.1 V AVDD 500 nA 400 mV 50 1000 μ ...
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... ADuCM360/ADuCM361 Parameter Test Conditions/Comments POWER-ON RESET (POR) POR Trip Level Refers to voltage at DVDD pin Power-on level Power-down level Timeout from POR WATCHDOG TIMER (WDT) Timeout Period 1 Timeout Step Size T3CON[3:2]=[10] FLASH/EE MEMORY 1 Endurance 11 Data Retention 12 Tj=85°C Digital Inputs All digital inputs ...
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... Total I for ADC includes figures for PGA≥32, input buffers, digital interface and the Sigma Delta modulator Min 1 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. J Rev Page ADuCM360/ADuCM361 Typ Max Unit 3-5 x Fclk 30.8 μs 3 ...
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... ADuCM360/ADuCM361 NOISE RESOLUTION OF PRIMARY AND AUXILIARY ADCS Table 2: RMS Noise (µV) vs. Gain and Output Update Rate (Using an Internal Reference (1.2V) Both ADCs) Update Rate (Hz) Gain of 1 3.75 (Chop On) 1.05 ADCxFLT = 0x8D7C 30 (Chop Off) 2.1 ADCxFLT = 0x007E 50 (Chop Off) 3.7 ADCxFLT = 0x007D 100 (Chop Off) 5.45 ADCxFLT = 0x004D ...
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... Chop Off 15.1 15.1 3906 Hz Sinc4 (12.4p-p) (12.4p-p) Gain of 2 Gain of 4 Gain of 8 0.5 0.27 0.17 1.4 0.85 0.44 2.2 0.92 0.46 2.8 1.25 0.63 5.0 2.5 1.2 7 3.5 1.75 10 5.7 2.6 70.0 35.0 17.2 ±250 mV ±125 mV (PGA = 4) (PGA = 8) 22.1 21.8 (19.4p-p) (19.1p-p) 20.5 20.5 (17.7p-p) (17.7p-p) 20.4 20.4 (17.7p-p) (17.7p-p) 19.9 19.9 (17.2p-p) (17.2p-p) 18.9 19 (16.2p-p) (16.3p-p) 18.4 18.4 (15.7p-p) (15.7p-p) 17.7 17.9 (15p-p) (15.2p-p) 15.1 15.1 (12.4p-p) (12.4p-p) Rev Page ADuCM360/ADuCM361 Gain of 16 Gain of 32 Gain of 64 0.088 0.07 0.06 0.27 0.22 0.19 0.3 0.21 0.2 0.38 0.32 0.28 0.75 0.7 0.57 1.2 0.83 0.77 1.71 1.3 1.24 8.9 4.8 2.65 ±62.5 mV ±31.25 mV ±15.625 mV (PGA = 16) (PGA = 32) (PGA = 64) 21.8 21.1 20.3 (19.1p-p) (18.4p-p) (17.6p-p) 20.1 19.4 18.6 (17.4p-p) (16.7p-p) (15.9p-p) 20 19.5 18.6 (17.3p-p) (16.8p-p) (15.9p-p) 19.6 18.9 18.1 (16.9p-p) (16.2p-p) (15.4p-p) 18.7 17.8 17.1 (15.9p-p) (15p-p) (14.3p-p) 18 17.5 16.6 (15.3p-p) (14.8p-p) (13.9p-p) 17.5 16.9 15.9 (14 ...
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... ADuCM360/ADuCM361 TIMING DIAGRAMS Capacitive load for each of the -bus line 400pF maximum as per timing is guaranteed by design and not production tested. 2 Table Timing in Fast Mode (400 kHz) Parameter Description t Serial Clock (SCL) low pulse width L t SCL high pulse width ...
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... UCLK 58 DAV MSB MSB IN t DSU t DHD Figure 3. SPI Master Mode Timing (PHASE Mode = 1) Rev Page ADuCM360/ADuCM361 Typ Max (SPIDIV + 1) × t UCLK (SPIDIV + 1) × t UCLK 0 35.5 12 35.5 12 35.5 12 35 BITS LSB ...
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... ADuCM360/ADuCM361 SCLK (POLARITY = 0) SCLK (POLARITY = 1) t DOSU MOSI MISO MSB IN t DSU Table 9. SPI Slave Mode Timing Parameter Description SCLK edge CS t SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge ...
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... Figure 5. SPI Slave Mode Timing (PHASE Mode = DAV MSB BITS BITS DHD Figure 6. SPI Slave Mode Timing (PHASE Mode = 0) Rev Page ADuCM360/ADuCM361 t SFS BITS LSB LSB IN t SFS LSB LSB IN ...
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... ADuCM360/ADuCM361 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter AVDD/IOVDD to GND Digital Input Voltage to DGND Digital Output Voltage to DGND V to AGND REF Analog Inputs to AGND Operating Temperature Range Storage Temperature Range Junction Temperature ESD (Human Body Model) rating All Pins θ Thermal Impedance JA 48-Pin LFCSP _VQ ...
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... AIN0 9 AIN1 10 AIN2 Figure 7. ADuCM360/ADuCM361 Pinout Description Reset. Input pin, active low. An internal pull-up is provided. General-Purpose Input and General-Purpose Output P2.1/ I pin may be the UART Data carrier Detect pin. This is a multi function input/output pin. General-Purpose Input and General Purpose Output P2.2/ Boot mode input select pin. When this pin is held low during any reset sequence, the part will enter UART download mode ...
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... ADuCM360/ADuCM361 Pin No. Mnemonic 11 AIN3 12 AIN4/IEXC 13 GND_SW 14 VREF+ 15 VREF− 16 AGND 17 AVDD 18 AVDD_REG 19 DAC 20 INT_REF 21 IREF 22 AIN5/IEXC 23 AIN6/IEXC 24 AIN7/VBIAS0/IEXC/EXT_REF2IN+ 25 AIN8/EXT_REF2IN- 26 AIN9 27 AIN10 28 AIN11/VBIAS1 29 P0.0/MISO1 30 P0.1/SCLK1/SCL/SIN 31 P0.2/MOSI1/SDA/SOUT 32 P0.3/IRQ0/ CS1 33 P0.4/RTS/ECLKO 34 P0.5/CTS/IRQ1 Description Differential or single ended modes. ADC Analog Input 3. This pin can be configured as a positive or negative input to either ADC in Differential or single ended modes ...
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... UART block only. This is a Triple function input/output pin. Serial Wire debug clock input pin. Serial Wire debug data input/output pin. **Exposed Paddle. The LFCSP_VQ has an exposed paddle that MUST BE connected to digital ground. Rev Page ADuCM360/ADuCM361 2 C Serial Clock Pin. Alternatively, ...
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... ADuCM360/ADuCM361 TYPICAL PERFORMANCE CHARACTERISTICS Figure 8. Common Mode Voltage (Vcm) in Volts vs Input Current in nA, Gain=4, ADC input 250mV, AVdd=3.6V, T=25C Figure 9. Common Mode Voltage (Vcm) in Volts vs Input Current in nA, Gain=128, ADC input 7.8125mV, AVdd=3.6V, T=25C ADC Codes 14000000 12000000 10000000 8000000 6000000 ...
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... MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. (CP-48-4) Figure 11. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad Dimensions shown in millimeters Rev Page ADuCM360/ADuCM361 48 1 5.20 EXPOSED PAD 5. 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO ...