AD9393/PCBZ AD [Analog Devices], AD9393/PCBZ Datasheet - Page 15

• Manufacturer Part Number: AD9393/PCBZ
• Description: Low Power HDMI Display Interface
• Manufacturer: AD [Analog Devices]

Hex Address
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x56
0x57
0x58
0x59
0x5A
0x5B
Read/Write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read
Read
Bits
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[6]
[3]
[2]
[7]
[6:4]
[3]
[2:0]
[6]
[5]
[4]
[2]
[1]
[0]
[6:0]
[3]
Default
Value
xxx01000
00000000
xxx01110
10000111
xxx11000
10111101
00110110
00110110
00110110
00100000
00001111
0xxxxxxx
x0xxxxxx
xxxx0xxx
xxxxx0xx
0
0
0
0
0
0
0
0
0
0
0
0
Register Name
CSC_COEFF_C2 MSB
CSC_COEFF_C2 LSB
CSC_COEFF_C3 MSB
CSC_COEFF_C3 LSB
CSC_COEFF_C4 MSB
CSC_COEFF_C4 LSB
TMDS PLL Control1
TMDS PLL Control2
TMDS PLL Control3
Test
Test
AV mute override
AV mute value
Disable video mute
Disable audio mute
MCLK PLL enable
MCLK PLL_N
N_CTS_DISABLE
MCLK FS_N
MDA/MCL PU
CLK term O/R
Manual CLK term
FIFO reset UF
FIFO reset OF
MDA/MCL three-state
Packet detected
HDMI mode
Rev. 0 | Page 15 of 40
Description
MSB of Register 0x48.
CSC coefficient for equation:
R
G
B
MSB of Register 0x4A.
CSC coefficient for equation:
R
G
B
MSB of Register 0x4C.
CSC coefficient for equation:
R
G
B
Must be written to 0x3B.
Must be written to 0x6D.
Must be written to 0x54.
Must be written to 0x20 for proper operation.
Must be written to 0x0F (default) for proper operation.
A1 overrides the AV mute value with Bit 6.
Sets AV mute value if override is enabled.
Disables mute of video during AV mute.
Disables mute of audio during AV mute.
MCLK PLL enable—uses analog PLL.
MCLK PLL_N [2:0]—this controls the division of the MCLK
out of the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4 …
Prevents the N/CTS packet on the link from writing to the N
and CTS registers.
Controls the multiple of 128 f
0 = 128 × f
This disables the MDA/MCL pull-ups.
Clock termination power-down override: 0 = auto,
1 = manual.
Clock termination: 0 = normal, 1 = disconnected.
This bit resets the audio FIFO if underflow is detected.
This bit resets the audio FIFO if overflow is detected.
This bit three-states the MDA/MCL lines.
These seven bits are updated if any specific packet has
been received since last reset or loss of clock detect.
Normal is 0x00.
Bit
0
1
2
3
4
5
6
0 = DVI, 1 = HDMI.
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= (A1 × R
= (C1 × R
= (A1 × R
= (C1 × R
= (A1 × R
= (C1 × R
= (B1 × R
= (B1 × R
= (B1 × R
Data Packet Detected
AVI infoframe.
Audio infoframe.
SPD infoframe.
MPEG source infoframe.
ACP packets.
ISRC1 packets.
ISRC2 packets.
S
, 1 = 256 × f
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + (A2 × G
) + (C2 × G
) + (A2 × G
) + (C2 × G
) + (A2 × G
) + (C2 × G
) + (B2 × G
) + (B2 × G
) + (B2 × G
S
, 2 = 384 × f
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + (B3 × B
) + (C3 × B
) + (B3 × B
) + (C3 × B
) + (B3 × B
) + (C3 × B
) + (A3 × B
) + (A3 × B
) + (A3 × B
S
used for MCLK out.
S
, 7 = 1024 × f
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + B4
) + C4
) + B4
) + C4
) + B4
) + C4
) + A4
) + A4
) + A4
AD9393
S
.