LT3435 LINER [Linear Technology], LT3435 Datasheet - Page 15

• Manufacturer Part Number: LT3435
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
ramp rate. When the current through the C
exceeds the C
output capacitor is limited by reducing the V
The C
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
Burst Mode OPERATION
To enhance efficiency at light loads, the LT3435 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LT3435 delivers short bursts of
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the
output capacitor. In addition, V
currents are reduced to typically 45µA and 125µA respec-
tively during the sleep time. As the load current decreases
towards a no load condition, the percentage of time that
the LT3435 operates in sleep mode increases and the
average input current is greatly reduced resulting in higher
efficiency.
dV
dt
SS
1V/DIV
=
V
OUT
threshold is proportional to the FB voltage (see
I
C
CSS
SS
V
V
I
L
IN
OUT
= 500mA
C
= 12V
CSS
SS
= 3.3V
= 1000pF
threshold (I
C
CSS
U
Figure 4. V
= 0.01µF
U
1ms/DIV
CSS
OUT
C
CSS
), the voltage ramp of the
dV/dt
IN
= 0.1µF
W
and BIAS quiescent
3435 F04
C
SS
pin voltage.
U
capacitor
During the sleep portion of the Burst Mode Cycle, the V
pin voltage is held just below the level need for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
The minimum average input current depends on the V
V
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
where
Example: For V
I
IN AVG
OUT
(
I
V
V
I
I
I
η = low current efficiency (non Burst Mode operation)
I
IN AVG
VINS
BIASS
FB
S
OUT
IN
(
= catch diode reverse leakage at V
ratio, V
= feedback network current
= input voltage
)
=
=
= input pin current in sleep mode
= output voltage
= BIAS pin current in sleep mode
)
45
45
≅
150
125
100
µ + µ +
µ + µ +
75
50
25
C
I
0
VINS
A
A
frequency compensation, feedback divider
0
OUT
5
5
+
10
= 3.3V, V
A
A
I
Figure 5. I
SHDN
INPUT VOLTAGE (V)
⎛
⎜
⎝
44
20
3 3
12
µ =
+
.
A
IN
⎛
⎜
⎝
⎞
⎟
⎠
30
Q
V
(
= 12V
125
V
vs V
OUT
99
IN
40
µ
µ +
IN
⎞
⎟
⎠
A
A
V
OUT
(
T
I
A
BIASS
50
OUT
= 25°C
12 5
= 3.3V
( . )
3435 F05
0 8
.
LT3435
60
( )
µ +
+
η
A
I
FB
15
0 5
+
.
I
S
IN
3435fa
µ
)
A
to
C
)