LT3437 LINER [Linear Technology], LT3437 Datasheet - Page 7

• Manufacturer Part Number: LT3437
• Description: High Voltage 500mA, 200kHz Step-Down Switching Regulator with 100uA Quiescent Current
• Manufacturer: LINER [Linear Technology]

PI FU CTIO S
SW (Pin 1/Pin 2): The SW pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
SW pin negative during switch off time. Negative voltage
is clamped with the external catch diode. Maximum nega-
tive switch voltage allowed is –0.8V.
NC (Pins 1, 3, 5, 7, 13, 16)(FE Package ONLY): No
Connection.
V
NPN switch. V
a voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V
BOOST (Pin 3/Pin 6): The BOOST pin is used to provide a
drive voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.8Ω FET
structure.
GND (Pins 4, 11/Pins 8, 17): The GND pin connection
acts as the reference for the regulated output, so load
regulation will suffer if the “ground” end of the load is not
at the same voltage as the GND pin of the IC. This
condition will occur when load current or other currents
flow through metal paths between the GND pin and the
load ground. Keep the path between the GND pin and the
load ground short and use a ground plane when possible.
The GND pin also acts as a heat sink and should be
soldered (along with the exposed leadframe) to the cop-
per ground plane to reduce thermal resistance (see Appli-
cations Information).
C
regulated output voltage determines the output voltage
ramp rate during start-up. When the current through the
C
age ramp of the output is limited. The C
proportional to the FB voltage (see Typical Performance
Characteristics) and is defeated for FB voltage greater than
0.9V (typical). See Soft-Start section in Applications Infor-
mation for details.
IN
SS
SS
U
(Pin 2/Pin 4): This is the collector of the on-chip power
capacitor exceeds the C
(Pin 5/Pin 9): A capacitor from the C
U
IN
powers the internal control circuitry when
CE
U
voltage across the internal NPN.
IN
(DD/FE)
pin through the input bypass
SS
threshold (I
SS
CSS
SS
threshold is
), the volt-
pin to the
BIAS (Pin 6/Pin 10): The BIAS pin is used to improve
efficiency when operating at higher input voltages and
light load current. Connecting this pin to the regulated
output voltage forces most of the internal circuitry to draw
its operating current from the output voltage rather than
the input supply. This architecture increases efficiency
especially when the input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is typically 3V.
V
amplifier and the input of the peak switch current com-
parator. It is normally used for frequency compensation,
but can also serve as a current clamp or control loop
override. V
maximum load. During the sleep portion of Burst Mode
operation, the V
burst threshold for better transient response. Driving the
V
into sleep mode.
FB (Pin 8/Pin 12): The feedback pin is used to determine
the output voltage using an external voltage divider from
the output that generates 1.25V at the FB pin. When the FB
pin drops below 0.9V, switching frequency is reduced, the
SYNC function is disabled and output ramp rate control is
enabled via the C
Applications Information for details.
SYNC (Pin 9/Pin 14): The SYNC pin is used to synchronize
the internal oscillator to an external signal. It is directly
logic compatible and can be driven with any signal be-
tween 25% and 75% duty cycle. The synchronizing range
is equal to maximum initial operating frequency up to
700kHz. When the voltage on the FB pin is below 0.9V the
SYNC function is disabled. When a synchronization signal
or logic-level high is present at the SYNC pin, Burst Mode
operation is disabled. See the synchronizing section in
Applications Information for details.
SHDN (Pin 10/Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to less than 1µA. The
SHDN pin requires a voltage above 1.3V with a typical
source current of 5µA to take the IC out of the shutdown
state.
Exposed Pad (Pin 11/Pin 17): Ground. Must be soldered
to the PCB.
C
C
(Pin 7/Pin 11): The V
pin to ground will disable switching and place the IC
C
sits at about 0.45V for light loads and 1.5V at
C
pin is held at a voltage slightly below the
SS
pin. See the Feedback section in
C
pin is the output of the error
LT3437
7
3437f