ADL5201-EVALZ AD [Analog Devices], ADL5201-EVALZ Datasheet - Page 6

• Manufacturer Part Number: ADL5201-EVALZ
• Description: Wide Dynamic Range, High Speed
• Manufacturer: AD [Analog Devices]

ADL5201
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1, 4, EP
2
3
5
6
7
8
9
10
11
12
13
14, 16
15, 17
18, 21,
22, 23, 24
19
20
Mnemonic
GND
VIN+
VIN−
MODE1
MODE0
SDIO/A5
SCLK/A4
GS1/CS/A3
GS0/FA/A2
UPDN_CLK/A1
UPDN_DAT/A0
LATCH
VOUT+
VOUT−
VPOS
PWUP
PM
Ground. The exposed paddle (EP) must be connected to a low impedance ground pad.
MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode.
LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode.
Power-Up Pin. A logic high (1.4 V ≤ PWUP ≤ 3.3 V) enables the part.
Description
Positive Input.
Negative Input.
Serial Data Input/Output (SDIO). When CS is pulled low, SDIO is used for reading and writing to the SPI port.
Bit 5 for Parallel Gain Control Interface (A5).
Serial Clock Input in SPI Mode (SCLK).
Bit 4 for Parallel Gain Control Interface (A4).
MSB for Gain Step Size Control in Up/Down Mode (GS1).
SPI Interface Select (CS). When serial mode is enabled, a logic low (0 V ≤ CS ≤ 0.8 V) enables the SPI interface.
Bit 3 for Parallel Gain Control Interface (A3).
LSB for Gain Step Size Control in Up/Down Mode (GS0).
Fast Attack (FA). In serial mode, a logic high (1.4 V ≤ FA ≤ 3.3 V) attenuates according to the FA setting in the SPI
word. Bit 2 for Parallel Gain Control Interface (A2).
Clock Interface for Up/Down Function (UPDN_CLK).
Bit 1 for Parallel Gain Control Interface (A1).
Data Pin for Up/Down Function (UPDN_DAT).
Bit 0 for Parallel Gain Control Interface (A0).
A logic low (0 V ≤ LATCH ≤ 0.8 V) allows gain changes. A logic high (1.4 V ≤ LATCH ≤ 3.3 V) disallows gain
changes.
Positive Output.
Negative Output.
Positive Power Supply.
Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high (1.4 V ≤ PM ≤ 3.3 V)
enables low power mode.
NOTES
1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO
A LOW IMPEDANCE GROUND PAD.
Figure 5. Pin Configuration
Rev. 0 | Page 6 of 28
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