ADL5324 AD [Analog Devices], ADL5324 Datasheet - Page 13

• Manufacturer Part Number: ADL5324
• Description: 400 MHz to 4000 MHz
• Manufacturer: AD [Analog Devices]

Data Sheet
APPLICATIONS INFORMATION
BASIC LAYOUT CONNECTIONS
The basic connections for operating the
in Figure 34. Table 6 lists the required matching components.
Capacitors C1, C2, and C3 are Murata GRM615 series (0402
size) High Q capacitors and C7 is a Murata GRM155 series
(0402 size). Inductor L1 is a Coilcraft 0603CS series (0603 size).
For all frequency bands, the placement of C1 and C2 are critical.
The placement of C3 becomes critical for the following bands:
1880 MHz to 1990 MHz, 2110 MHz to 2170 MHz, 2300 MHz to
2400 MHz, 2570 MHz to 2690 MHz. and 3500 MHz to 3600 MHz.
For operation from 420 MHz to 494 MHz, 728 MHz to 768 MHz,
and 869 MHz to 960 MHz, R2 is replaced with a Coilcraft (0402
size) High Q inductor. Table 7 lists the recommended component
placement for various frequencies.
A 5 V dc bias is supplied through L1, which is connected to
RFOUT (Pin 3). In addition to C4, 10 nF and 10 µF power supply
decoupling capacitors are also required. The typical current
consumption for the
RFIN
1
2
3
SEE THE RECOMMENDED COMPONENTS FOR BASIC CONNECTIONS TABLE
SEE TABLE 6 FOR RECOMMENDED COMPONENT SPACING.
C1, C2, AND C3 ARE MURATA HIGH Q CAPACITORS GRM615 SERIES.
FOR FREQUENCY-SPECIFIC COMPONENTS.
R1
0Ω
2.4pF
C3
3
C1
2pF
λ1
3
2
Figure 34. Basic Connections
ADL5324
1
ADL5324
(2)
2
is 133 mA.
3
GND
VSUP
ADL5324
L1
15nH
C6 10µF
C5 10nF
C4 100pF
λ2
2
C2
2.2pF
R2
0Ω
3
are shown
20pF
C7
RFOUT
Rev. B | Page 13 of 20
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 35 shows the recommended land pattern for the ADL5324.
To minimize thermal impedance, the exposed paddle on the
SOT-89 package underside is soldered to a ground plane along
with Pin 2. If multiple ground layers exist, they should be
stitched together using vias. For more information on land
pattern design and layout, refer to the Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP).
This land pattern, on the
a measured thermal resistance (θ
the temperature at the top of the SOT-89 package is found with
an IR temperature gun. Thermal simulation suggests a junction
temperature 10°C higher than the top of package temperature.
With additional ambient temperature and I/O power
measurements, θ
5.56mm
0.20mm
Figure 35. Recommended Land Pattern
JA
0.86mm
could be determined.
1.50mm
ADL5324
1.80mm
3.00mm
JA
) of 37°C/W. To measure θ
evaluation board, provides
0.62mm
ADL5324
1.27mm
3.48mm
JA
,