ADL5523_09 AD [Analog Devices], ADL5523_09 Datasheet - Page 17

• Manufacturer Part Number: ADL5523_09
• Description: 400 MHz to 4000 MHz Low Noise Amplifier
• Manufacturer: AD [Analog Devices]

EVALUATION BOARD
Figure 53 shows the schematic of the ADL5523 evaluation board.
The board is powered by a single supply, and dc bias can be
applied to the board through clip-on leads at VPOS and GND
or through a 2-pin connector, W1.
The evaluation board comes optimized at 1950 MHz from the
factory, but it can be easily modified to work at any frequency
between 400 MHz and 4 GHz. Table 7 lists the recommended
components at various frequencies.
Table 7. Recommended Components and Positions of Matching Components for Basic Connections Tuned for Optimal Noise
Frequency
(MHz)
500
900
1300
1950
2140
2600
3500
1
2
3
4
5
The Murata GJM High-Q series capacitor is recommended for C1.
The Coilcraft High Q 0403HQ or 0402HP inductors are recommended for L1 and L2.
If R2 = 8 Ω, reduce R1 to 600 Ω.
If R2 = 8 Ω, use a high power resistor (0.2 W rating minimum).
Note that at 3500 MHz, a capacitor, not an inductor, is used at L1.
RFIN
C1
Figure 54. Evaluation Board Layout (Top View)
L1
C1
(Size
0402)
Open
2.4 pF
2.7 pF
1.6 pF
1.6 pF
0.75 pF
0.5 pF
Figure 53. Evaluation Board Schematic
1
1 VBIAS
2 RFIN
3 NC
4 NC
C2
(Size
0402)
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
ADL5523
R1
Z1
RFOUT
C3
(Size
0402)
Open
Open
1.0 nF
1.0 nF
1.0 nF
1.0 nF
1.0 nF
VPOS
NC
NC
VPOS
8
7
6
5
TR1
TR2
C4
(Size
0402)
Open
Open
Open
Open
Open
Open
Open
R2
L2
100nF
DNP
W1
C5
C4
C3
C2
0Ω
RFOUT
C5
(Size
0402)
100 nF
100 nF
100 nF
100 nF
100 nF
100 nF
100 nF
GND
L1
(Size
0403)
9 nH
8.2 nH
3.4 nH
1.0 nH
1.0 nH
1.0 nH
2.4 pF
Rev. A | Page 17 of 24
2
5
L2
Size
0403)
12 nH
3.4 nH
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
2
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 56 shows the recommended land pattern for ADL5523.
To minimize thermal impedance, the exposed pad on the
package underside is soldered down to a ground plane. If
multiple ground layers exist, they are stitched together using
vias (a minimum of five vias is recommended). Pin 3 to Pin 6
can be left unconnected or can be connected to ground. For
more information on land pattern design and layout, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
R1
(Size
0603)
1.3 kΩ
1.3 kΩ
1.3 kΩ
1.3 kΩ
1.3 kΩ
1.3 kΩ
1.3 kΩ
3
Figure 55. Evaluation Board Layout (Bottom View)
0.71mm
R2
(Size
0603)
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
1
4
Figure 56. Recommended Land Pattern
4
TR1
(mm)
0
0
0
2.5 × 0.6
5.0 × 0.6
8.0 × 0.6
7.0 × 0.6
2.03mm
1.53mm
TR2
(mm)
0
0
8.0 × 0.6
5.5 × 0.6
3.0 × 0.6
0
1 × 0.6
C1
Position
C1
C1
C1
C1
C1
C1
C1
8
5
ADL5523
C3
Position
N/A
N/A
6
C3
4
2
1