ADL5592-EVALZ AD [Analog Devices], ADL5592-EVALZ Datasheet - Page 13

• Manufacturer Part Number: ADL5592-EVALZ
• Description: 250 MHz to 2400 MHz RF Variable Gain Amplifier
• Manufacturer: AD [Analog Devices]

Table 4. 10-Bit Gain Words for SPI Port
D9
0
0
0
0
0
1
1
0
0
0
0
0
0
1
Table 5. Timing Requirements for the SPI Port
Mnemonic
t
t
t
t
f
CLK
0
1
2
3
D8
0
0
0
0
1
0
1
0
0
0
0
0
0
1
ATTN 2
D7
0
0
0
1
0
0
1
0
0
0
0
0
0
1
to all bits in the serial data stream
Description
Latch enable setup time. Time between latch enable active (high) and first rising edge of serial clock.
Serial data setup time. Time between valid serial data and rising clock edge. Note that this time applies
Serial data hold time. Time after rising clock edge during which the serial data line cannot change in
value. Note that this time applies to all bits in the serial data stream
Latch enable hold time. Time after final falling clock edge during which the latch enable must remain
active (high).
Clock period.
DATA
CLK
D6
0
0
1
0
0
0
1
0
0
0
0
0
0
1
LE
1
0
1
0
1
0
D5
0
1
0
0
0
0
1
0
0
0
0
0
0
1
D4
0
0
0
0
0
0
0
0
0
0
0
1
1
1
t
0
D3
0
0
0
0
0
0
0
0
0
0
1
0
1
1
LOAD DATA INTO
SERIAL REGISTER
ON RISING EDGE.
t
1
ATTN 1
D2
0
0
0
0
0
0
0
0
0
1
0
0
1
1
Figure 19. Timing Diagram of SPI Port Transmission
D0
t
2
D1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
Rev. 0 | Page 13 of 20
D0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
ATTN 1 (dB)
0
0
0
0
0
0
0
1
2
4
8
16
31
31
D9
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL LATCHES
ON LE FALLING EDGE.
ATTN 2 (dB)
0
1
2
4
8
16
31
0
0
0
0
0
0
31
Resulting Attenuation
t
3
Total Attenuation (dB)
0
1
2
4
8
16
31
1
2
4
8
16
31
62
Min
15
15
15
15
ADL5592
Max
15
Unit
ns
ns
ns
MHz
ns