CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet - Page 30

• Manufacturer Part Number: CS8405A-IS
• Description: 96 kHz Digital Audio Interface Transmitter
• Manufacturer: CIRRUS [Cirrus Logic]

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OMCK
ISCLK
ILRCK
SDIN
SFMT0
SFMT1
APMS
TCBLD
TCBL
CEN
V
U
COPY/C 1 COPY Channel Status Bit/C Bit (Input) - In hardware mode A (CEN = 0), the COPY/C and ORIG
EMPH
AUDIO
ORIG
21 Master Clock ( Input ) - The frequency must be only 256x the sample rate.
13 Serial Audio Bit Clock ( Input / Output ) - Serial bit clock for audio data on the SDIN pin.
12 Serial Audio Input Left/Right Clock ( Input / Output ) - Word rate clock for the audio data on the
14 Serial Audio Data Port ( Input ) - Audio data serial input pin.
10 Serial Audio Data Port Master/Slave Select ( Input ) - APMS should be connected to VL+ to set
11 Transmit Channel Status Block Direction ( Input ) - Connect TCBLD to VL+ to set TCBL as an out-
15 Transmit Channel Status Block Start ( Input / Output ) - When operated as output, TCBL is high dur-
16 C Bit Enable ( Input ) - Determines how the channel status data bits are input. When CEN is low,
17 Validity Bit ( Input ) - In hardware modes A and B, the V pin input determines the state of the validity
18 User Data Bit ( Input ) - In hardware modes A and B, the U pin input determines the state of the user
19 Audio Channel Status Bit ( Input ) - In hardware mode A (CEN = 0), the AUDIO pin determines the
28 ORIG Channel Status Bit Control ( Input ) - In hardware mode A (CEN = 0), the ORIG and COPY/C
4
5
3 Pre-Emphasis Indicator ( Input ) - In hardware mode A (CEN = 0), the EMPH pin low sets the 3
SDIN pin.
Serial Audio Data Format Select ( Input ) - Selecta the serial audio input port format. See Table 3.
serial audio input port as a master or connected to DGND to set the port as a slave.
put. Connect TCBLD to DGND to set TCBL as an input.
ing the first sub-frame of a transmitted channel status block, and low at all other times. When oper-
ated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-
frame to be the start of a channel status block.
hardware mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter
selected channel status data. When CEN is high, hardware mode B is selected, where the COPY/C
pin is used to enter serial channel status data.
bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
stream, see Table 2. In hardware mode B, the COPY/C pin becomes the direct C bit input data pin.
emphasis channel status bits to indicate 50/15 ms pre-emphasis of the transmitted audio data. If
EMPH is high, then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.
state of the audio/non audio Channel Status bit in the outgoing AES3 data stream.
pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
stream, see Table 2.
CS8405A
DS469F2