BU64240GWZ ROHM [Rohm], BU64240GWZ Datasheet - Page 3

• Manufacturer Part Number: BU64240GWZ
• Description: Silicon Monolithic Integrated Circuit
• Manufacturer: ROHM [Rohm]

Package Outline
I2C BUS Format (Fast mode: SCL=400kHz )
W2W1W0
Register
D9～D0
W rite m ode（R /W = 0)
R ead m ode
name
Fig.1 UCSP30L1 Package (Unit: mm)
PS
EN
M
S
S
S
S : start signal
A : acknow ledge
0
0
0
Operating parameter1
Operating parameter2
Operating parameter3
Operating parameter4
0
0
0
Mode select signal
Serial power save
Register address
OUT pin status
0
0
0
Limit Voltage
Setting item
1
1
1
1
1
1
R ead
W rite
0
0
0
O utput from M aster
P : stop signal
nA : non acknow ledge
0
0
0
R /W
Side View
Top View
Bottom View
0
1
'0' = Standby mode, '1' = Operating mode
'0' = Hi-impedance, '1' = Constant current sink.
'0' = ISRC Mode Disabled, '1' = ISRC Mode Enabled
‘000’ = Limit Voltage setting, '001' = Operating parameter setting1
‘010’ = Operating parameter setting2, ‘011’ = Operating parameter setting 3
‘100’ = Operating parameter setting4
Target position DAC code[D9:D0]
Resonance frequency setting[D7:D3], Slew rate speed setting[D1:D0]
VCM un-control current setting1[D9:D0]
VCM un-control current setting2[D9:D0]
Step resolution[D7:D5] ( Minimum step resolution = 1LSB@10bit_DAC)
Step time setting[D4:D0] ( Minimum step time resolution = 50us )
A P S EN W 2 W 1 W 0 M D 9 D 8 A D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A
A P S EN W 2 W 1 W 0 M ※ ※ A
A P S EN W 2 W 1 W 0 M
REV. A
O utput from Slave
※ : D on`t care
Pin Arrangement (Top View)
Block Diagram
SDA
SCL
PS
C D 9 C D 8
Fig.2 BU64240GWZ Pin Arrangement (Top View)
BandGap
OSC
slew rate control
A
B
A
Description
Power Save
Fig.3 BU64240GWZ Block Diagram
Interface
I2C bus
C D 7 C D 6 C D 5 C D 4 C D 3 C D 2 C D 1 C D 0
&
OUT
PS
10bit DAC
1
VREF
U pdate W (register address)
10
0.1～10uF
GND
SCL
2
TSD
Pre Driver
VCC
&
UVLO
SDA
VCC
convertor
3
V/I
BandGap
A
U pdate
GND
VCC
RNF
=0.5
Ω
OUT
VCC
3/5
I
SINK