ADCMP580_05 AD [Analog Devices], ADCMP580_05 Datasheet

ADCMP580_05

Manufacturer Part Number

ADCMP580_05

Description

Ultrafast SiGe Voltage Comparators

Manufacturer

AD [Analog Devices]

Datasheet

1.ADCMP580_05.pdf (16 pages)

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FEATURES

180 ps propagation delay

25 ps overdrive and slew rate dispersion

8 GHz equivalent input rise time bandwidth

100 ps minimum pulse width

37 ps typical output rise/fall

10 ps deterministic jitter (DJ)

200 fs random jitter (RJ)

−2 V to +3 V input range with +5 V/−5 V supplies

On-chip terminations at both input pins

Resistor-programmable hysteresis

Differential latch control

Power supply rejection > 70 dB

APPLICATIONS

Automatic test equipment (ATE)

High speed instrumentation

Pulse spectroscopy

Medical imaging and diagnostics

High speed line receivers

Threshold detection

Peak and zero-crossing detectors

High speed trigger circuitry

Clock and data signal restoration

GENERAL DESCRIPTION

The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage

comparators fabricated on Analog Devices’ proprietary XFCB3

Silicon Germanium (SiGe) bipolar process. The ADCMP580

features CML output drivers; the ADCMP581 features reduced

swing ECL (negative ECL) output drivers; and the ADCMP582

features reduced swing PECL (positive ECL) output drivers.

All three comparators offer 180 ps propagation delay and

100 ps minimum pulse width for 10 Gbps operation with

200 fs random jitter (RJ). Overdrive and slew rate dispersion

are typically less than 15 ps.

The ±5 V power supplies enable a wide −2 V to +3 V input

range with logic levels referenced to the CML/NECL/PECL

outputs. The inputs have 50 Ω on-chip termination resistors

with the optional capability to be left open (on an individual

pin basis) for applications requiring high impedance input.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

ADCMP580/ADCMP581/ADCMP582

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

The CML output stage is designed to directly drive 400 mV

into 50 Ω transmission lines terminated to ground. The NECL

output stages are designed to directly drive 400 mV into 50 Ω

terminated to −2 V. The PECL output stages are designed to

directly drive 400 mV into 50 Ω terminated to V

High speed latch and programmable hysteresis are also

provided. The differential latch input controls are also 50 Ω

terminated to an independent V

CML or ECL or to PECL logic.

The ADCMP580/ADCMP581/ADCMP582 are available in

a 16-lead LFCSP package.

NONINVERTING

INVERTING

TERMINATION

INPUT

FUNCTIONAL BLOCK DIAGRAM

HYS

Voltage Comparators

ADCMP580/

ADCMP581/

ADCMP582

Figure 1.

Ultrafast SiGe

pin to interface to either

LE INPUT

CML/ECL/

PECL

www.analog.com

CCO

− 2 V.

Q OUTPUT

Related parts for ADCMP580_05

ADCMP580_05 Summary of contents

Page 1

FEATURES 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) −2 ...

Page 2

ADCMP580/ADCMP581/ADCMP582 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Information ......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Considerations.............................................................. 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Typical Application Circuits.......................................................... 10 Application Information................................................................ 11 REVISION ...

Page 3

SPECIFICATIONS −5 +3 CCI EE CCO Table 1. Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Range Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias ...

Page 4

ADCMP580/ADCMP581/ADCMP582 Parameter ADCMP582 (PECL) Output Voltage High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Low Level Output Voltage Differential AC PERFORMANCE Propagation Delay Propagation Delay Tempco Prop Delay ...

Page 5

TIMING INFORMATION Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the terms shown in the figure. LATCH ENABLE LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT Table 2. Timing Descriptions Symbol ...

Page 6

ADCMP580/ADCMP581/ADCMP582 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter SUPPLY VOLTAGES Positive Supply Voltage (V to GND) CCI Negative Supply Voltage (V to GND) EE Logic Supply Voltage (V to GND) CCO INPUT VOLTAGES Input Voltage Differential Input Voltage Input Voltage, Latch ...

Page 7

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN INDICATOR 12 GND ADCMP580 TOP VIEW (Not to Scale GND TN Figure 3. ADCMP580 Pin Configuration Table ...

Page 8

ADCMP580/ADCMP581/ADCMP582 TYPICAL PERFORMANCE CHARACTERISTICS = − CCI EE CCO 12 10 VIN COMMON-MODE BIAS SWEEP –4 –2 0 COMMON MODE (V) Figure 6. Bias ...

Page 9

LOT2 CHAR1 RISE –3 LOT2 CHAR1 FALL LOT3 CHAR1 RISE –4 LOT3 CHAR1 FALL –5 –2 – (V) CM Figure 12. ADCMP580 Prop Delay vs. Common-Mode Voltage M1 M1 ...

Page 10

ADCMP580/ADCMP581/ADCMP582 TYPICAL APPLICATION CIRCUITS ADCMP580 LATCH INPUTS Figure 17. Zero-Crossing Detector with CML Outputs ADCMP581 LATCH INPUTS Figure ...

Page 11

APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCMP58x family of comparators is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance critically important to use low impedance supply ...

Page 12

ADCMP580/ADCMP581/ADCMP582 OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power, and ground impedances or other layout issues can severely limit performance and ...

Page 13

COMPARATOR HYSTERESIS Adding hysteresis to a comparator is often desirable in a noisy environment or when the differential inputs are very small or slow moving. The transfer function for a comparator with hysteresis is shown in Figure 28. If the ...

Page 14

ADCMP580/ADCMP581/ADCMP582 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 0.90 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range ADCMP580BCP-WP −40°C to +125°C ADCMP580BCP–R2 −40°C to +125°C ADCMP580BCP–RL7 −40°C to +125°C ADCMP581BCP-WP −40°C to +125°C ADCMP581BCP–R2 −40°C to +125°C ADCMP581BCP–RL7 −40°C ...

Page 15

NOTES ADCMP580/ADCMP581/ADCMP582 Rev Page ...

Page 16

ADCMP580/ADCMP581/ADCMP582 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04672-0-7/05(0) Preliminary Technical Data Rev Page ...

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