ADCMP606 AD [Analog Devices], ADCMP606 Datasheet - Page 9

• Manufacturer Part Number: ADCMP606
• Description: Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP606 and ADCMP607 comparators are very high
speed devices. Despite the low noise output stage, it is essential
to use proper high speed design techniques to achieve the
specified performance. Because comparators are
uncompensated amplifiers, feedback in any phase relationship is
likely to cause oscillations or undesired hysteresis. Of critical
importance is the use of low impedance supply planes,
particularly the output supply plane (V
plane (GND). Individual supply planes are recommended as
part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the V
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the V
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
CML-COMPATIBLE OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved by using proper transmission line terminations. The
outputs of the ADCMP606 and ADCMP607 are designed to drive
400 mV directly into a 50 Ω cable or into transmission lines
terminated using either microstrip or strip line techniques with
50 Ω referenced to V
simplified schematic diagram in Figure 14. Each output is back-
terminated with 50 Ω for best transmission line matching.
CC
pin. High frequency bypass capacitors should be
Figure 14. Simplified Schematic Diagram of
CML-Compatible Output Stage
CC
. The CML output stage is shown in the
16mA
V
GND
CCO
50Ω
CCO
Q
Q
) and the ground
CCI
and V
CCO
supply
Rev. PrA | Page 9 of 16
If these high speed signals must be routed more than a
centimeter, then either microstrip or strip line techniques are
required to ensure proper transition times and to prevent
excessive output ringing and pulse-width-dependent
propagation delay dispersion.
It is also possible to operate the outputs with only the internal
termination if greater output swing is desired. This can be
especially useful for driving inputs on CMOS devices intended
for full swing ECL and PECL. V
that the specified minimum output low level (see the Electrical
Characteristics section) is not violated and the line length
driven is as short as possible.
USING/DISABLING THE LATCH FEATURE
The latch input of the ADCMP607 is designed for maximum
versatility. It can safely be left floating, or it can be driven low by
any standard TTL/CMOS device as a high speed latch.
In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 Ω, allowing the comparator hysteresis to be
easily controlled by either a resistor or an inexpensive CMOS DAC.
Driving this pin high or floating the pin removes all hysteresis.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
parallel to the hysteresis control resistor or current source.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of V
ADCMP606/ADCMP607
CCO
must be kept high enough
CC
.