X98024L128-3.3 INTERSIL [Intersil Corporation], X98024L128-3.3 Datasheet - Page 28
X98024L128-3.3
Manufacturer Part Number
X98024L128-3.3
Description
240MHz Triple Video Digitizer with Digital PLL
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.X98024L128-3.3.pdf
(29 pages)
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Signals from
the Host
SDA Bus
Signals from
the X98024
A7
D7
1
1
A6
D6
0
0
X98024 Serial Bus Address
X98024 Serial Bus Address
R
A5
S
T
A
T
D5
0
0
1 0 0 1 1 0 A 0
Serial Bus
Address
START Command
(Repeat if desired)
START Command
STOP Command
28
A4
D4
1
1
C
A
K
A3
a a a a a a a a
D3
1
1
Register
Address
FIGURE 16. CONFIGURATION REGISTER READ
0
A2
0
D2
A
C
K
(pin 48)
(pin 48)
R
E
S
A
R
T
T
A1
D1
1 0 0 1 1 0 A 1
A
A
Serial Bus
Address
X98024
R/W
A0
R/W
D0
0
1
A
C
K
d d d d d d d d
X98024 Serial Bus Address Write
This is the 7 bit address of the X98024 on the 2 wire bus. The
address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R/W = 0,
indicating next transaction will be a write.
Signals the beginning of serial I/O
X98024 Register Address Write
This sets the initial address of the X98024’s configuration
register for subsequent reading
X98024 Serial Bus Address Write
This is the 7 bit address of the X98024 on the 2 wire bus. The
address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R/W = 1,
indicating next transaction(s) will be a read.
Ends the previous transaction and starts a new one
X98024 Register Data Read(s)
This is the data read from the X98024’s configuration register.
Note: The X98024’s Configuration Register’s address pointer auto
increments after each data read: repeat this step to read multiple
sequential bytes of data from the Configuration Register.
Signals the ending of serial I/O
Read*
Data
A
C
K
O
S
T
P
* The data read step may be repeated to read
from the X98024’s Configuration Register
sequentially, beginning at the Register
Address written in the two steps previous.
June 6, 2005
FN8220.0