MAX8833_09 MAXIM [Maxim Integrated Products], MAX8833_09 Datasheet - Page 10

• Manufacturer Part Number: MAX8833_09
• Description: Dual, 3A, 2MHz Step-Down Regulator
• Manufacturer: MAXIM [Maxim Integrated Products]

Dual, 3A, 2MHz Step-Down Regulator
The power-good, open-drain output for regulator 2
(PWRGD2) is high impedance when V
V
EN2 is low, V
load protection is activated, or when V
The MAX8833 has an external reference input. Connect
an external reference between 0 and V
REFIN to set the FB1 regulation voltage. To use the inter-
nal 0.6V reference, connect REFIN to SS1. When the IC
is shut down, REFIN is pulled to GND through 335Ω.
The MAX8833 features separate enable inputs (EN1
and EN2) for the two regulators. Driving EN_ high
enables the corresponding regulator; driving EN_ low
turns the regulator off. Driving both EN1 and EN2 low
puts the IC in low-power shutdown mode, reducing the
supply current typically to 30nA. The MAX8833 regula-
tors power up when the following conditions are met
(see Figure 2):
•
•
•
•
•
Once these conditions are met, the MAX8833 begins
soft-start. FB2 regulates to the voltage at SS2. During
soft-start, the SS2 capacitor is charged with a constant
8µA current source so that its voltage ramps up for the
Figure 3a. Startup and Sequencing Options—Two Independent Output Startup and Shutdown Waveforms
10
FB2
EN_ is logic-high.
V
V
The internal reference is powered.
The IC is not in thermal overload (T
______________________________________________________________________________________
VDD
IN_
≥ 0.9 x V
is above the UVLO threshold.
is above the UVLO threshold.
VDD
External Reference Input (REFIN)
SS2
or V
. PWRGD2 is low when V
IN2
is below V
Startup and Sequencing
UVLO
FB2
, the thermal-over-
J
SS2
< 0.9 x V
< +165°C).
VDD
≥ 0.54V and
SS2
- 1.6V to
< 0.54V,
SS2
.
soft-start time. See the Setting the Soft-Start Time sec-
tion to select the SS2 capacitor for the desired soft-start
time. FB1 regulates to the voltage at REFIN. Connect
REFIN to SS1 to use the internal reference with soft-
start time set independently by the SS1 capacitor (see
Figure 3a).
Figure 2. Startup Control Diagram
EN1
EN2
RRUVB
RRUVB
PWRGD1
PWRGD2
UVLO
UVLO
IN1
IN2
OUT2
OUT1
EN1
EN2
UVLO
UVLO
10kΩ
10kΩ
THERM
THERM
SHDN
SHDN
BIAS
GEN
REF
TLIM
TLIM
PWRGD1
PWRGD2
V
SS1
DD
RDY
REF
REG1 ON
REG2 ON
REFIN
EN2
EN1
SS2
UVLO
V
DD
RRUVB
EN1
EN2