MAX8833_09 MAXIM [Maxim Integrated Products], MAX8833_09 Datasheet - Page 7

• Manufacturer Part Number: MAX8833_09
• Description: Dual, 3A, 2MHz Step-Down Regulator
• Manufacturer: MAXIM [Maxim Integrated Products]

15, 16, 17
24, 25, 26
13, 14
18, 19
22, 23
PIN
10
11
12
20
21
1
2
3
4
5
6
7
8
9
PWRGD1
PWRGD2
COMP2
PGND2
PGND1
FSYNC
NAME
REFIN
BST2
BST1
GND
N.C.
V
VDL
SS2
FB2
EN2
LX2
LX1
IN2
DD
_______________________________________________________________________________________
Power-Good Open-Drain Output for Regulator 1. PWRGD1 is high impedance when V
V
thermal shutdown is activated, or when V
External Reference Input for Regulator 1. Connect an external reference to REFIN, or connect REFIN to SS1
to use the internal reference. REFIN is discharged to GND through 335Ω when EN1 is low or regulator 1 is
shut down due to a fault condition.
Supply Voltage. Connect a 10Ω resistor from V
Analog Ground. Connect GND to the analog ground plane. Connect the analog and power ground planes
together at a single point near the IC.
No Connection
Supply Voltage Input for Low-Side Gate Drive. Connect VDL to IN_ or the highest available supply voltage
less than 3.6V. Connect a 1µF capacitor from VDL to the power ground plane.
Frequency Set and Synchronization. Connect a 4.75kΩ to 20.5kΩ resistor from FSYNC to GND to set
switching frequency or drive with a 250kHz to 2.5MHz clock signal to synchronize switching.
R
Power-Good Open-Drain Output for Regulator 2. PWRGD2 is high impedance when V
≥ 0.9 x V
shutdown is activated, or when V
S oft- S tar t for Reg ul ator 2. C onnect a cap aci tor fr om S S 2 to GN D to set the soft- star t ti m e. S ee the S etti ng the S oft-
S tar t Ti m e secti on. S S 2 i s i nter nal l y p ul l ed l ow w i th 335Ω w hen E N 2 i s l ow or r eg ul ator 2 i s i n a faul t cond i ti on.
Feedback Input for Regulator 2. Connect FB2 to the center of an external resistor-divider from the output to
GND to set the output voltage from 0.6V to 90% of V
Compensation for Regulator 2. COMP2 is the output of the internal voltage-error amplifier. Connect external
compensation network from COMP2 to FB2. See the Compensation Design section. COMP2 is internally
pulled to GND when the output is shut down.
Enable Input for Regulator 2. Drive EN2 high to enable regulator 2, or drive low for shutdown. For always-on
operation, connect EN2 to V
Power-Supply Input for Regulator 2. The voltage range is 2.35V to 3.6V. Connect two 10µF and one 0.1µF
ceramic capacitors from IN2 to PGND2.
Power Ground for Regulator 2. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
Inductor Connection for Regulator 2. Connect an inductor between LX2 and the regulator output. LX2 is high
impedance when the IC is shut down.
Bootstrap Connection for Regulator 2. Connect a 0.1µF capacitor from BST2 to LX2. BST2 is the supply for
the high-side gate drive. BST2 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX2 to BST2 and from VDL to BST2.
Bootstrap Connection for Regulator 1. Connect a 0.1µF capacitor from BST1 to LX1. BST1 is the supply for
the high-side gate drive. BST1 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX1 to BST1 and from VDL to BST1.
Inductor Connection for Regulator 1. Connect an inductor between LX1 and the regulator output. LX1 is high
impedance when the IC is shut down.
Power Ground for Regulator 1. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
FB1
FSYNC
≥ 0.9 x V
Dual, 3A, 2MHz Step-Down Regulator
= (T - 0.05µs) x (10kΩ/0.95µs), where T is the oscillator period.
SS2
. PWRGD2 is low when V
REFIN
. PWRGD1 is low when V
DD
.
FB2
SS2
< 0.9 x V
< 0.54V, EN2 is low, V
FB1
REFIN
< 0.9 x V
SS2
DD
FUNCTION
.
to VDL and connect a 0.1µF capacitor from V
< 0.54V, EN1 is low, V
IN2
REFIN
. FB2 is high impedance when the IC is shut down.
.
DD
or IN2 is below UVLO, the thermal
DD
or IN1 is below UVLO, the
Pin Description
REFIN
SS2
≥ 0.54V and V
≥ 0.54V and
DD
to GND.
FB2
7