25LC040A-E/MC MICROCHIP [Microchip Technology], 25LC040A-E/MC Datasheet - Page 11
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25LC040A-E/MC
Manufacturer Part Number
25LC040A-E/MC
Description
4K SPI Bus Serial EEPROM
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.25LC040A-EMC.pdf
(28 pages)
2.6
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS regis-
ter as shown in Table 2-2. See Figure 2-7 for the WRSR
timing sequence. Four levels of protection for the array
are selectable by writing to the appropriate bits in the
STATUS register. The user has the ability to write-protect
none, one, two or all four of the segments of the array as
shown in Table 2-3.
FIGURE 2-7:
© 2007 Microchip Technology Inc.
SCK
Note:
CS
SO
SI
Write Status Register Instruction
(WRSR)
An internal write cycle (T
sequence.
0
0
0
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
1
0
2
Instruction
0
3
WC
0
4
) is initiated on the rising edge of CS after a valid write STATUS register
0
5
High-impedance
0
6
1
7
25AA040A/25LC040A
TABLE 2-3:
7
8
BP1
0
0
1
1
6
9
Data to STATUS Register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
12
3
13
2
Array Addresses
Write-Protected
(180h-1FFh)
(100h-1FFh)
(000h-1FFh)
upper 1/4
14
upper 1/2
1
DS21827D-page 11
none
all
15
0