AT24C32-10SC ATMEL [ATMEL Corporation], AT24C32-10SC Datasheet - Page 4

• Manufacturer Part Number: AT24C32-10SC
• Description: 2-Wire Serial EEPROM
• Manufacturer: ATMEL [ATMEL Corporation]

AC Characteristics
Applicable over recommended operating range from T
pF (unless otherwise noted).
Note:
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
4
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Endurance
SCL
LOW
HIGH
I
AA
BUF
HD.STA
SU.STA
HD.DAT
SU.DAT
R
F
SU.STO
DH
WR
1. This parameter is characterized and is not 100% tested.
(1)
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free
before a new transmission can start
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25 C, Page Mode
AT24C32/64
(1)
(1)
(1)
(1)
A
= -40 C to +85 C, V
Min
200
100
4.7
4.0
0.1
4.7
4.0
4.7
4.7
1M
0
1.8-volt
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32/64 features a low power
standby mode which is enabled: a) upon power-up and b)
after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.
Max
100
100
300
4.5
1.0
20
CC
Min
200
100
4.7
4.0
0.1
4.7
4.0
4.7
4.7
1M
2.7-, 2.5-volt
0
= +1.8V to +5.5V, CL = 1 TTL Gate and 100
Max
100
100
300
4.5
1.0
10
Min
100
1.2
0.6
0.1
1.2
0.6
0.6
0.6
1M
50
0
5.0-volt
Max
400
300
0.9
0.3
50
10
Write Cycles
Units
kHz
ms
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s