AT25128-10CC-1.8 ATMEL [ATMEL Corporation], AT25128-10CC-1.8 Datasheet - Page 7

• Manufacturer Part Number: AT25128-10CC-1.8
• Description: SPI Serial EEPROMs
• Manufacturer: ATMEL [ATMEL Corporation]

Functional Description
The AT25128 is designed to interface directly with the syn-
chronous serial peripheral interface (SPI) of the 6805 and
68HC11 series of microcontrollers.
The AT25128 utilizes an 8 bit instruction register. The list
of instructions and their operation codes are contained in
Table 1. All instructions, addresses, and data are trans-
ferred with the MSB first.
Table 1. Instruction Set for the AT25128
WRITE ENABLE (WREN):
the write disable state when V
ming instructions must therefore be preceded by a Write
Enable instruction.
WRITE DISABLE (WRDI):
against inadvertent writes, the Write Disable instruction
disables all programming modes. The WRDI instruction is
independent of the status of the WP pin.
READ STATUS REGISTER (RDSR):
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
Table 2a. Status Register Format
Instruction
Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
WPEN
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X
Instruction
Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
X
X
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
The device will power up in
BP1
CC
To protect the device
is applied. All program-
BP0
The Read Status
WEN
RDY
Table 2b. Read Status Register Bit Definition
WRITE STATUS REGISTER (WRSR):
struction allows the user to select one of four levels of pro-
tection. The AT25128 is divided into four array segments.
One quarter (1/4), one half (1/2), or all of the memory seg-
ments can be protected. Any of the data within any se-
lected segment will therefore be READ only. The block
write protection levels and corresponding status register
control bits are shown in Table 3.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same properties and functions as the regular
memory cells (e.g. WREN, t
Table 3. Block Write Protect Bits
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the WP pin is low and the WPEN bit
is “1.” Hardware write protection is disabled when either
the WP pin is high or the WPEN bit is “0.” When the device
is hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are dis-
abled. Writes are only allowed to sections of the memory
which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it
cannot be changed back to “0,” as long as the WP pin is
held low.
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 4.
Bits 0-7 are 1s during an internal write cycle.
1(1/4)
2(1/2)
3(All)
Level
0
BP1 BP0
Register
0
0
1
1
Status
Bits
0
1
0
1
Definition
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle is
in progress.
Bit 1= 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
See Table 3.
See Table 3.
Array Addresses Protected
WC
, RDSR).
3000 - 3FFF
2000 - 3FFF
0000 - 3FFF
AT25128
AT25128
None
The WRSR in-
(continued)
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