AT88SC1003-09PT-00 ATMEL [ATMEL Corporation], AT88SC1003-09PT-00 Datasheet
AT88SC1003-09PT-00
Related parts for AT88SC1003-09PT-00
AT88SC1003-09PT-00 Summary of contents
Page 1
... After personalization of the memory by the issuer, an internal fuse is blown that secures critical memory areas of the device and configures the IC for use by the end customer. The action of blowing this fuse is irreversible. The AT88SC1003 is manufactured using low-power CMOS technology. EEPROM programming func- tions are accomplished using an internally generated high-voltage pump for single voltage supply operation ...
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... Pin Descriptions Supply Voltage (VCC) Serial Clock (CLK) Serial Data (I/O) Reset (RST) Program (PGM) Fuse (FUS) AT88SC1003 2 Figure 1. Card Module Contact RST = C2 CLK = C3 FUS = C4 Figure 2. Block Diagram V CC Power On GND Reset RST Address CLK Counter PGM FUS The VCC input is a 4.5V-to-5.5V positive voltage. ...
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... Logic “0” Logic “1” Logic “1” AT88SC1003 die and modules are delivered with the issuer fuse intact. Issuer personal- ization is completed at this level. Security code validation is required to allow access to personalize the EEPROM memory. During personalization, the manufacturer fuse may be blown to lock the manufacturer’ ...
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... Memory Map Table 2. AT88SC1003 Memory Diagram Bit Address Zone 0–15 FZ – Fabrication Zone 16–79 IZ – Issuer Zone 80–95 SC – Security Code 96–111 SCAC – Security Code Attempts Counter (only first 4 bits used) 112–175 CPZ – Code Protected Zone 176–431 AZ1 – ...
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... The security code is initially set by Atmel to protect the product during transportation to the card SC (16 bits) issuer. During personalization, this code must be entered and verified by the AT88SC1003 to allow access to the changed in either security mode. The security code gives access to Application Zones 1, 2, and 3, and also gives access to the code-protected zone area for erase and write. Verification of the security code will set the internal flag SV to “ ...
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... After the issuer fuse is blown, the state of the EC2EN fuse is locked and cannot be changed. Issuer Fuse This EEPROM bit functions as a fuse that is used to change the security mode of the AT88SC1003 (16 bits) from Security Mode 1 (“1”), to Security Mode 2 (“0”). Initialization of the IC for use by the end customer occurs in Security Mode 1 ...
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... Address location 1584 is designated as the erase bit for Application Zone 3. The erase protocol for an Erase Bit EB3 AT88SC1003 in Security Mode 2 requires that the erase key (EZ3) be verified, then an erase (1 bit) operation must be executed on the next bit following the erase key. This action will result in erasing the entire zone ...
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... Word Sixteen consecutive data bits. A word boundary will begin on an address that is evenly divisible by 16. The AT88SC1003 will allow words to be written to a “0” during personal- ization (Security Level 1). Erase operations will always operate on 16-bit words when applied to addresses outside the application zones. ...
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... This validation operation requires the user to find a bit in the SCAC, addresses 96–99, that is a logic “1”. A write is performed followed by an erase. The AT88SC1003 will validate that the comparison was correct by outputting a logic “1”, and SV will be set. After the erase, all 16 bits in the SCAC will also be erased ...
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... Table 4. Definition of AT88SC1003 Internal Flags (Continued) Flag Definition E1 Application Zone 1 Erase Flag E2 Application Zone 2 Erase Flag with Erase Counter Operation Enabled (EC2EN FUSE = “1”) E2 Application Zone 2 Erase Flag with Erase Counter Operation Disabled (EC2EN FUSE = “0”) E3 Application Zone 3 Erase ...
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... Issuer Fuse This fuse is used to personalize the AT88SC1003 for end customer use addi- tional EEPROM bit that can be programmed to a logic “0”. This is its “blown” state. Security of the device when the issuer fuse is a logic “1” is described in Table 6 on page 12 ...
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... FUS Pin = “1” “1” after validation of the security code 3. 2nd bit of the Application Zone 1 (Bit 177) 4. 2nd bit of the Application Zone 2 (Bit 481) 5. 2nd bit of the Application Zone 3 (Bit 1025) 6. Manufactuer fuse = “0” when blown. AT88SC1003 12 (4) (5) (6) R2 ...
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... AT88SC1003 (1) (10) (11 Read Erase x x yes yes yes x x yes yes yes x x yes ...
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... The internal address counter counts up to 1599. An additional CLK pulse resets the address to “0”. AT88SC1003 14 The AT88SC1003 circuit micro operation modes are selected by the input logic levels on the control pins PGM, RST, and CLK and by the internal address. Timing for these oper- ations is specified in Table 11 on page 19. ...
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... With CLK low, a falling edge on the RST pin will reset the address counter to address 0. FUNCTION: The address is reset to “0”, and the first bit of the memory is driven by the AT88SC1003 on I/O after a reset. E1, E2, and E3 are reset when the address is reset to “0”. The reset operation has no effect on any of the other flags (SV, P1, P2, P3, R1, R2, R3) ...
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... Application Zones 1, 2, and 3 can be erased when “1” AZ3 OPERATION: Security Mode 1 Increment address counter to any bit within AZ1, AZ2, or AZ3. Perform “Erase Operation Sequence” as specified above. FUNCTION: This operation will erase the entire application zone. AT88SC1003 16 2035B–SMEM–08/03 ...
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... Blowing Issuer Set address counter between Address 992 and 1007. Fuse SV must be set. The FUS pin can be either a “0” “1”. RST pin = “0” Perform a write operation. Issuer fuse will logic “0” state. 2035B–SMEM–08/03 AT88SC1003 17 ...
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... V Input Low Level IL V Input High Level IH V Output Low Level ( mA Input Leakage Current LI I I/O Leakage Current ( AT88SC1003 18 NOTE: + 0.7V CC Applicable over recommended operating range from +70°C (unless otherwise noted µ kHz) OL CLK ...
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... DH t 2.2 SPR t 0.2 HPR The circuit has an output with open drain. An external resistor is necessary between VCC and I/O in order to load the output 0.3 and AT88SC1003 Typ Max – – – – – 2.0 – – – – – 2.0 – – ...
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... AC Load Circuit Timing Diagrams AT88SC1003 20 Figure 3. AC Load Circuit VCC R LOAD Test Point 100 pF Test Ckt. Included Figure 4. Reset Address CLK t RH RST I/O Output Note: CLK should be low on the falling edge of RST. CLK may remain low while RST is pulsed. CHIP I/O 0 (internal address counter) ...
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... During any erase or write operation, PGM must fall before the falling edge of CLK at the end of t (recommend a minimum setup time of 1 usec). CHP After the rising edge of PGM to initiate the erase/write operation, delay at least t usec) before driving data on the I/O contact. AT88SC1003 t CLK ...
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... AT88SC1003 22 Figure 7. Compare Address A n-1 CLK t SC Input I/O Note: Input data is latched on the falling edge of CLK. Comparison occurs on the next falling edge of CLK. The address counter is incremented on the falling edge of CLK. Figure 8. INC/CMP (before code presentation) Address A n-1 CLK t SC Hi-Z Output Input I/O Note: After the rising edge of CLK on the address immediately preceding the security code or erase keys, the I/O will be disabled (Hi-Z) ...
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... Figure 9. Security Code Validation 2035B–SMEM–08/03 AT88SC1003 23 ...
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... C = After the falling edge of CLK, the device will drive the I/O contact to the logic state of the existing data in Bit 480. The state of this bit is not affected by the AZ1 erase operation After the falling edge of CLK, the address is incremented and the state of the next bit is driven on the I/O contact. AT88SC1003 24 Compare EZ1 ...
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... D = After the falling edge of CLK, the address is incremented and the state of the next bit is driven on the I/O contact. 2035B–SMEM–08/03 Compare EZ2 ( 735 736 737 736 737 Input Input = Compare data (input). n AT88SC1003 Erase ( 766 768 767 CD 1 767 Output Input Read (C) (D) A 769 D 768 Output 25 ...
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... Figure 12. Erase Operation Application Zone 2 (AZ2) EC2 Function Enabled AT88SC1003 26 2035B–SMEM–08/03 ...
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... The E3 flag will be reset to “0” when the reset function is executed, or when the address is incremented beyond Address 1599. 2035B–SMEM–08/03 Compare EZ3 1535 1536 1537 1536 1537 1 Input = Compare data (input). n AT88SC1003 Erase (A) ( 1582 1583 1584 CD 1 1538 Input Output Input 27 ...
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... Ordering Information Ordering Code AT88SC1003-09ET-00 AT88SC1003-09PT-00 AT88SC1003-10WI-00 (1) Package Type Description M2 – E Module M2 ISO 7816 Smart Card Module M2 – P Module M2 ISO 7816 Smart Card Module with Atmel Logo Note: 1. Formal drawings may be obtained from an Atmel Sales Office. AT88SC1003 28 Package Voltage Range M2 – E Module M2 – ...
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... The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the mod- ule after excise or punching from the carrier tape are generally 0.4 mm greater in both directions (i.e., a punched M2 module will yield 13.0 x 11.8 mm). 2035B–SMEM–08/03 Ordering Code: 09PT-00 8.0 [mm] AT88SC1003 Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Square - 8.8 x 8.8 [mm] Thickness: 0.58 [mm] Pitch: 14.25 mm ...
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... Atmel Corporation 2003. All rights reserved. Atmel of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 ...