AT25DF641A-MH-T ATMEL [ATMEL Corporation], AT25DF641A-MH-T Datasheet - Page 39

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AT25DF641A-MH-T

Manufacturer Part Number
AT25DF641A-MH-T
Description
64-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
11.3
8693A–DFLASH–8/10
Write Status Register Byte 2
Figure 11-2. Write Status Register Byte 1
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Sta-
tus Register. Using the Write Status Register Byte 2 command is the only way to modify the
RSTE and SLE bits in the Status Register during normal device operation, and the SLE bit can
only be modified if the sector lockdown state has not been frozen. Before the Write Status Reg-
ister Byte 2 command can be issued, the Write Enable command must have been previously
issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the
opcode of 31h must be clocked into the device followed by one byte of data. The one byte of
data consists of three don’t care bits, the RSTE bit value, the SLE bit value, and three additional
don’t care bits (see
ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status Register will be
modified, and the WEL bit in the Status Register will be reset back to a logical “0”. The SLE bit
will only be modified if the Freeze Sector Lockdown State command has not been previously
issued.
The complete one byte of data must be clocked into the device before the CS pin is deasserted,
and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise,
the device will abort the operation, the state of the RSTE and SLE bits will not change, and the
WEL bit in the Status Register will be reset back to the logical “0” state.
Table 11-4.
Bit 7
X
Write Status Register Byte 2 Format
SCK
Bit 6
SO
CS
X
SI
Table
11-4). Any additional data bytes that are sent to the device will be
Bit 5
X
MSB
HIGH-IMPEDANCE
0
0
Atmel AT25DF641A [Preliminary]
0
1
0
2
OPCODE
0
RSTE
3
Bit 4
0
4
0
5
0
6
1
7
MSB
D
Bit 3
SLE
8
STATUS REGISTER IN
X
9
D
10 11
BYTE 1
D
D
12
Bit 2
D
13
X
X
14 15
X
Bit 1
X
Bit 0
X
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