AT49LL080-33JC ATMEL [ATMEL Corporation], AT49LL080-33JC Datasheet - Page 8

• Manufacturer Part Number: AT49LL080-33JC
• Description: 8-megabit Low-pin Count Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 1. LPC Read Waveforms
Table 5. LPC Read Cycle
Note:
8
Clock Cycle
LFRAME
LAD[3:0]
13 - 14
3 - 10
11
12
15
16
17
18
19
CLK
1
2
1. Field contents are valid on the rising edge of the present clock cycle.
AT49LL080
START
1
Field Name
CYCTYPE
WSYNC
RSYNC
CYCTYPE
START
ADDR
+ DIR
TAR0
TAR1
DATA
DATA
TAR0
TAR1
+ DIR
2
3
4
5
Field Contents
0000b (READY)
0101b (WAIT)
ADDR
1111b (float)
1111b (float)
6
LAD[3:0]
0000b
010xb
1111b
1111b
YYYY
YYYY
YYYY
7
8
(1)
9
10
Float then OUT
Float then
Direction
LAD[3:0]
then float
then float
11 12 13
TAR
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
SYNC(3)
14
Comments
LFRAME must be active (low) for the part to respond.
Only the last start field (before LFRAME transitioning
high) should be recognized. The START field contents
indicate an LPC memory read cycle.
Cycle Type: Indicates the type of cycle. Bits 3:2 must
be 01 for a memory cycle.
DIR: Bit 1 indicates the direction of the transfer (0 for
read). Bit 0 is reserved.
These eight clock cycles make up the 32-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most significant nibble first.
In this clock cycle, the master (ICH) has driven the
bus to all 1s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle”.
The LPC takes control of the bus during this cycle.
During the next clock cycle, it will be driving “sync
data”.
The LPC outputs the value 0101, a wait-sync
(WSYNC, a.k.a. “short-sync”), for two clock cycles.
This value indicates to the master (ICH) that data is
not yet available from the part. This number of wait-
syncs is a function of the device’s access time.
During this clock cycle, the LPC will generate a
“ready-sync” (RSYNC) indicating that the least
significant nibble of the least significant byte will be
available during the next clock cycle.
YYYY is the least significant nibble of the least
significant data byte.
YYYY is the most significant nibble of the least
significant data byte.
The LPC Flash memory drives LAD0 - LAD3 to 1111b
to indicate a turnaround cycle.
The LPC Flash memory floats its outputs, the master
(ICH) takes control of LAD3 - LAD0.
15 16
DATA
17
18 19
TAR
3273C–FLASH–5/03