AT28HC256N-12JI ATMEL [ATMEL Corporation], AT28HC256N-12JI Datasheet - Page 4

• Manufacturer Part Number: AT28HC256N-12JI
• Description: 256 (32K x 8) High-speed Parallel EEPROM
• Manufacturer: ATMEL [ATMEL Corporation]

SDP is enabled by the host system issuing a series of three write commands; three spe-
cific bytes of data are written to three specific addresses (refer to “Software Data
Protection” algorithm). After writing the 3-byte command sequence and after t
the
WC
entire AT28HC256N will be protected against inadvertent write operations. It should be
noted, that once protected the host may still perform a byte or page write to the
AT28HC256N. This is done by preceding the data to be written by the same 3-byte com-
mand sequence.
Once set, SDP will remain active unless the disable command sequence is issued.
Power transitions do not disable SDP and SDP will protect the AT28HC256N during
power-up and power-down conditions. All command sequences must conform to the
page write timing specifications. It should also be noted that the data in the enable and
disable command sequences is not written to the device and the memory addresses
used in the sequence may be written with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the three byte command
sequence will start the internal write timers. No data will be written to the device; how-
ever, for the duration of t
, read operations will effectively be polling operations.
WC
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the
user for device identification. By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH the additional bytes may be written to or read from in the same man-
ner as the regular memory array.
OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte soft-
ware code. Please see “Software Chip Erase” application note for details.
AT28HC256N
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