M95010-R STMICROELECTRONICS [STMicroelectronics], M95010-R Datasheet - Page 24

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M95010-R

Manufacturer Part Number
M95010-R
Description
4 Kbit, 2 Kbit and 1 Kbit Serial SPI bus EEPROM with high speed Clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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Power-up and delivery states
7
7.1
7.2
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Power-up and delivery states
Power-up state
After Power-up, the device is in the following state:
The BP1 and BP0 bits of the Status Register are unchanged from the previous power-down
(they are non-volatile bits).
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Block Protect (BP1
and BP0) bits are initialized to 0.
low power Standby Power mode
deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
not in the Hold Condition
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
M95040, M95020, M95010

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