M34D64-R STMICROELECTRONICS [STMicroelectronics], M34D64-R Datasheet - Page 5

• Manufacturer Part Number: M34D64-R
• Description: 64 Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Quarter of Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

DEVICE OPERATION
The device supports the I
summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter,
and any device that reads the data to be a
receiver. The device that controls the data transfer
is known as the bus master, and the other as the
slave device. A data transfer can only be initiated
by the bus master, which will also provide the
serial clock for synchronization. The M34D64
device is always a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and
driven
communication between the device and the bus
master. A Read command that is followed by
NoAck can be followed by a Stop condition to force
the device into the Stand-by mode. A Stop
condition at the end of a Write command triggers
the internal EEPROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a
successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases
Serial Data (SDA) after sending eight bits of data.
During the 9
Table 5. Operating Modes
Note: 1. X =
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
High.
V
Mode
IH
th
or V
clock pulse period, the receiver pulls
A
IL
.
Stop
condition
2
C protocol. This is
RW bit
1
0
1
1
0
0
terminates
WC
V
V
X
X
X
X
IL
IL
1
Serial Data (SDA) Low to acknowledge the receipt
of the eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is
driven Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received on
Serial Data (SDA), the device only responds if the
Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Bytes
1
1
1
32
1
th
bit is the Read/Write bit (RW). This bit is
2
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
START, Device Select, RW = 0
C bus. Each one is given a unique 3-bit
Initial Sequence
th
bit time. If the
M34D64
5/21