M34D64-W_08 STMICROELECTRONICS [STMicroelectronics], M34D64-W_08 Datasheet - Page 14

• Manufacturer Part Number: M34D64-W_08
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Device operation
3.6
14/27
Figure 7.
Write operations
Following a Start condition the bus master sends a Device Select Code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in
sequences with WC = 0 (data write
responds to each address byte with an acknowledge bit, and then waits for the data byte(s).
Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write
instruction with Write Control (WC) driven high (during a period of time from the Start
condition until the end of the two address bytes) will not modify the contents of the top
quarter of the memory.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte
Bits b15 to b0 form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10
bit” time slot), either at the end of a Byte Write or a Page Write, the internal EEPROM Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
(Table 3.: Most significant
Write mode sequences with WC = 0 (data write enabled)
ACK
Dev sel
Dev sel
Data in N
byte) is sent first, followed by the Least Significant Byte (
R/W
R/W
ACK
ACK
enabled), and waits for two address bytes. The device
ACK
Byte addr
Byte addr
ACK
ACK
Byte addr
Byte addr
ACK
ACK
Figure 7.: Write mode
Data in 1
Data in
ACK
ACK
AI01106d
Data in 2
M34D64-W
:
th
).