M24128-BR3BN6T STMICROELECTRONICS [STMicroelectronics], M24128-BR3BN6T Datasheet - Page 6

• Manufacturer Part Number: M24128-BR3BN6T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24256-B, M24128-B
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
that is the most significant memory address bits
(b14-b6 for the M24256-B and b13-b6 for the
M24128-B) are the same. If more bytes are sent
than will fit up to the end of the row, a condition
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
6/19
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont’d)
PAGE WRITE
(cont’d)
NO ACK
DEV SEL
DEV SEL
DATA IN N
R/W
R/W
ACK
ACK
th
NO ACK
bit” time
BYTE ADDR
BYTE ADDR
ACK
ACK
BYTE ADDR
BYTE ADDR
A STOP condition at any other time does not trig-
ger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
DATA IN 2
AI01120B