M24128-BR3BN6T STMICROELECTRONICS [STMicroelectronics], M24128-BR3BN6T Datasheet - Page 7

• Manufacturer Part Number: M24128-BR3BN6T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 6. Write Mode Sequences with WC=0 (data write enabled)
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
– Step 2: if the memory is busy with the internal
followed by a Device Select Code (the first byte
of the new instruction).
write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-
minated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont’d)
PAGE WRITE
(cont’d)
w
) is shown in Table 9, but the
DEV SEL
DEV SEL
ACK
DATA IN N
R/W
R/W
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
ACK
ACK
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the mas-
ter sends another START condition, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowl-
edges this, and outputs the byte addressed by the
BYTE ADDR
BYTE ADDR
ACK
ACK
DATA IN 1
DATA IN
ACK
ACK
M24256-B, M24128-B
DATA IN 2
AI01106B
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