CY14B101K CYPRESS [Cypress Semiconductor], CY14B101K Datasheet - Page 3

• Manufacturer Part Number: CY14B101K
• Description: 1 Mbit (128K x 8) nvSRAM With Real-Time Clock
• Manufacturer: CYPRESS [Cypress Semiconductor]

Device Operation
The CY14B101K nvSRAM is made up of two functional
components paired in the same physical cell, a SRAM memory
cell and a nonvolatile QuantumTrap cell. The SRAM memory
cell operates as a standard fast static RAM. Transfer of the
data can be from the SRAM to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture allows all cells to be
stored and recalled in parallel. During the STORE and
RECALL operations SRAM READ and WRITE operations are
inhibited. The CY14B101K supports infinite reads and writes
just like a typical SRAM. In addition, it provides infinite
RECALL operations from the nonvolatile cells and up to
200,000 STORE operations.
SRAM READ
The CY14B101K performs a READ cycle whenever CE and
OE are low, while WE and HSB are high. The address
specified on pins A
bytes will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay of t
(READ cycle 1). If the READ is initiated by CE or OE, the
outputs will be valid at t
(READ cycle 2). The data outputs repeatedly responds to
address changes within the t
for transitions on any control input pins. It remains valid until
another address change, or until CE or OE is brought high, or
WE or HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable before
entering the WRITE cycle and must remain stable until either
CE or WE goes high, at the end of the cycle. The data on the
common IO pins DQ
data is valid t
before the end of an CE-controlled WRITE. It is recommended
that OE be kept high during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left low,
internal circuitry turns off the output buffers t
goes low.
AutoStore Operation
The CY14B101K stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store activated by HSB, Software Store activated by an
address sequence, and AutoStore on device power down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101K.
During normal operation, the device draws current from V
to charge a capacitor connected to the V
charge will be used by the chip to perform a single STORE
operation. If the voltage on the V
the part automatically disconnects the V
STORE operation will be initiated with power provided by the
V
Figure 1 shows the proper connection of the storage capacitor
(V
Electrical Characteristics,” on page 14
Document #: 001-06401 Rev. *E
CAP
CAP
capacitor.
) for automatic store operation. Refer to the
SD
before the end of a WE-controlled WRITE or
0-16
0–7
determines which of the 131,072 data
will be written into the memory if the
ACE
AA
or at t
access time without the need
CC
pin drops below V
DOE
for the size of V
CAP
, whichever is later
CAP
pin from V
pin. This stored
HZWE
Table , “DC
PRELIMINARY
after WE
SWITCH
CC
CAP
. A
CC
AA
,
.
The voltage on the V
internal to the chip. A pull up must be placed on WE to hold it
inactive during power up.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. Monitor the HSB signal by the system to detect if
an AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B101K provides the HSB pin for controlling and
acknowledging the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY14B101K conditionally initiates a STORE operation
after t
the SRAM took place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven low to indicate a busy condition while the STORE
(initiated by any means) is in progress.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14B101K continues SRAM operations for
t
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, t
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
During any STORE operation, regardless of how it was
initiated, the CY14B101K continues to drive the HSB pin low,
releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY14B101K remains
disabled until the HSB pin returns high. Leave the HSB
unconnected if it is not used.
DELAY
DELAY
. During t
. An actual STORE cycle only begins if a WRITE to
DELAY
Figure 1. AutoStore Mode
CAP
, multiple SRAM READ operations may
V
CAP
pin is driven to 5V by a charge pump
DELAY
, to complete. However, any
V
WE
CY14B101K
CC
Page 3 of 24
V
CC
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