CY14B101LA CYPRESS [Cypress Semiconductor], CY14B101LA Datasheet
CY14B101LA
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CY14B101LA Summary of contents
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... Features ■ 20 ns, 25 ns, and 45 ns Access Times ■ Internally Organized as 128K x 8 (CY14B101LA) or 64K x 16 (CY14B101NA) ■ Hands off Automatic STORE on Power Down with only a Small Capacitor ■ STORE to QuantumTrap Nonvolatile Elements Initiated by Software, Device Pin, or AutoStore on Power Down ■ ...
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... DQ6 DQ7 28 DQ5 27 DQ4 DQ3 CY14B101LA, CY14B101NA [ [ BHE BLE TSOP [8] 10 ...
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... Power AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to CAP Supply nonvolatile elements Connect No Connect. This pin is not connected to the die. Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY Figure 3. Pin Diagram - 54-Pin TSOP HSB 1 [7] ...
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... HSB goes LOW are inhibited until HSB SWITCH returns HIGH. In case the write latch is not set, HSB is not driven . A STORE CC capacitor. LOW by the CY14B101LA/CY14B101NA. But any SRAM read CAP and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. CY14B101LA, CY14B101NA pin, AutoStore ...
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... H Notes 9. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A Rest of the address lines are don’t care. 10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. ...
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... STORE and write operations. The low voltage condition is detected when V CY14B101LA/CY14B101NA write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after t active). This protects against inadvertent writes during power up or brown out conditions. ...
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... NV pattern (that is, complex 4-byte pattern hex or more random bytes) as part of the final system manufac- turing test to ensure these system routines work consistently. Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY ■ Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While ...
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... Max, V < V < Max, V < V < > OUT < – pin and Rated CAP SS CY14B101LA, CY14B101NA = 25°C) ....................................................1.0W Ambient Temperature V CC 0°C to +70°C 2.7V to 3.6V –40°C to +85°C [11] Min Typ Max 2.7 3.0 3 ...
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... CC Test Conditions 54-TSOP II 48-SSOP 44-TSOP II Test conditions follow standard 30.73 test methods and procedures for measuring thermal impedance, 6.08 in accordance with EIA/JESD51. Figure 5. AC Test Loads 3.0V OUTPUT 789Ω CY14B101LA, CY14B101NA Min Unit 20 Years 200 K Max Unit 32-SOIC Unit °C/W TBD 31 ...
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... Min Max Address Valid OHA CY14B101LA, CY14B101NA Unit Min Max Min Max ...
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... Data Output I Standby CC Figure 8. SRAM Write Cycle #1: WE Controlled Address CE BHE, BLE WE Data Input Data Output Previous Data Note 21 must be > V during address transitions. IH Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY Address Valid ACE LZCE t DOE t LZOE t DBE ...
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... Figure 9. SRAM Write Cycle #2: CE Controlled Address CE BHE, BLE WE Data Input Data Output Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled Address CE BHE, BLE WE Data Input Data Output Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY [3, 17, 18, 21 Address Valid SCE PWE t ...
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... Figure 11. AutoStore or Power Up RECALL 23 t Note STORE t HHHD t LZHSB t DELAY t HRECALL Read & Write BROWN POWER-UP OUT RECALL AutoStore SWITCH. SWITCH. CY14B101LA, CY14B101NA Min Max Min Max 2.65 2.65 150 150 1.9 1 500 500 [27 Note ...
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... DELAY Note Figure 13. Autostore Enable/Disable Cycle t RC Address # HZCE Table 2 on page 5. WE must be HIGH during all six consecutive cycles. time. DELAY CY14B101LA, CY14B101NA Min Max Min Max 200 200 [28] ...
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... HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low DHSB DHSB [29, 30] Figure 15. Soft Sequence Processing t Soft Sequence SS Command Address #6 Address # CY14B101LA, CY14B101NA Min Max Min Max 100 100 t HHHD t LZHSB only by Internal ...
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... L Data In (DQ –DQ ); Write –DQ in High Data In (DQ –DQ ); Write –DQ in High CY14B101LA, CY14B101NA Mode Power Standby Active Active Active Mode Power Standby Active Active Active Active Active Active Active Active Active Active Page [+] Feedback ...
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... Pin Blank - 32/44/48 Die revision: Blank: No Rev Rev NVSRAM 14 - AutoStore + Software STORE + Hardware STORE Cypress Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY Option Tape and Reel Blank - Std. Temperature Commercial (0 to 70° Industrial (–40 to 85°C) Package TSOP SSOP ...
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... CY14B101LA-SZ25XC CY14B101NA-ZS25XCT CY14B101NA-ZS25XC CY14B101NA-ZSP25XCT CY14B101NA-ZSP25XC CY14B101LA-ZS25XIT CY14B101LA-ZS25XI CY14B101LA-SP25XIT CY14B101LA-SP25XI CY14B101LA-SZ25XIT CY14B101LA-SZ25XI CY14B101NA-ZS25XIT CY14B101NA-ZS25XI CY14B101NA-ZSP25XIT CY14B101NA-ZSP25XI Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY Package Package Type Diagram 51-85087 44-pin TSOP II 51-85087 44-pin TSOP II 51-85061 48-pin SSOP 51-85061 48-pin SSOP 51-85127 32-pin SOIC 51-85127 ...
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... CY14B101LA-SZ45XIT CY14B101LA-SZ45XI CY14B101NA-ZS45XIT CY14B101NA-ZS45XI CY14B101NA-ZSP45XIT CY14B101NA-ZSP45XI All parts are Pb-free. This table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts. Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY Package Package Type Diagram 51-85087 44-pin TSOP II 51-85087 44-pin TSOP II ...
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... Document #: 001-42879 Rev. *C PRELIMINARY Figure 16. 44-Pin TSOP II (51-85087) PIN 1 I. BASE PLANE 0°-5° 0.10 (.004) 0.597 (0.0235) 0.406 (0.0160) SEATING PLANE CY14B101LA, CY14B101NA DIMENSION IN MM (INCH) MAX MIN EJECTOR PIN BOTTOM VIEW 10.262 (0.404) 10 ...
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... Package Diagrams (continued) Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY Figure 17. 48-Pin SSOP (51-85061) Figure 18. 32-Pin SOIC (51-85127) 51-85061 *C Page [+] Feedback ...
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... Package Diagrams (continued) Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY Figure 19. 54-Pin TSOP II (51-85160) 51-85160-** Page [+] Feedback ...
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... Document History Page Document Title: CY14B101LA, CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM Document Number: 001-42879 Submission Orig. of Rev. ECN No. Date Change ** 2050747 See ECN UNC/PYRS *A 2607447 11/14/2008 GVCH/AESA *B 2654484 02/05/09 GVCH/PYRS Document #: 001-42879 Rev. *C CY14B101LA, CY14B101NA PRELIMINARY Description of Change New Data Sheet Removed 15 ns access speed Updated “ ...
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... Document Title: CY14B101LA, CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM Document Number: 001-42879 Submission Orig. of Rev. ECN No. Date Change *C 2733909 07/09/09 GVCH/AESA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at www ...