HYB18H1G321AF QIMONDA [Qimonda AG], HYB18H1G321AF Datasheet - Page 24

• Manufacturer Part Number: HYB18H1G321AF
• Description: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

4.2.6
The address and command termination is used to set the value of the internal termination resistors. The GDDR3 DRAM
supports ZQ / 4, ZQ / 2 and ZQ termination values. The mode register programming overwrites the programming during the
chip initialization.
4.2.7
The GDDR3 DRAM can be internally configured as two 512Mbit (2-CS mode) or one 1Gbit device (1-CS mode). The pins CS1
and A12 are only active in two, resp. 1-CS mode and act either as the chip select for the second rank, or the row-address for
the upper 4k-row-address range. If bit A2 from EMRS2 (“Merged Mode”) is set to 1 then the 2 operations mode will be inverted.
Note also that at 1000 MHz speed grade only 1-CS mode is supported.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Operation Mode
0
1
DQ[7:0]
A[9:0],
A11
CLK#
Com.
RDQS
CLK
A10
EMRS
Add
0
Address command termination
Operation mode
N/D
1
t
RIDon
N/D
2
Merged Mode = 0
one-CS
two-CS
N/D
3
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
N/D
4
24
N/D
Operation Mode Function of defined Merged Mode
5
Vendor Code and Revision ID
EMRS
Add
6
N/D
7
Merged Mode = 1
two-CS
one-CS
t
RIDoff
Add:
N/D:
EMRS: Extended Mode Register Set Command
N/D
8
Don't Care
Address
NOP or Deselect
HYB18H1G321AF–10/11/14
N/D
9
Internet Data Sheet
FIGURE 12
TABLE 10
N/D
1-Gbit GDDR3
10