HYB18L256160B QIMONDA [Qimonda AG], HYB18L256160B Datasheet
HYB18L256160B
Available stocks
Related parts for HYB18L256160B
HYB18L256160B Summary of contents
Page 1
...
Page 2
... HYB18L256160B[C/F]-7.5, HYE18L256160B[C/F]-7.5, HYE18L256160BCL-7.5, HYE18L256160BFL-7.5 Revision History: 2006-09, Rev. 1.73 Page Subjects (major since last revision) All Qimonda update Previous Revision: 2005-07, Rev. 1.72 added disclaimer 53 Rev. 1.71: deleted -BCX and BFX product types Previous Revision: Rev Table 25: Updated 8 Chapter 2.1: added to note 6: Programming of the Extended Mode Register... ...
Page 3
... Clock Cycle Time ( ) CKmin Item Banks Rows Columns Rev. 1.73, 2006-09 01302004-CZ2R-J9SE V = 1.65V to 1.95V DDQ DD2 DD3 - 7.5 133 9.5 Addresses BA0, BA1 A0 - A12 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM TABLE 1 Performance Unit MHz TABLE 2 Memory Addressing Scheme ...
Page 4
... HYB18L256160BC-7.5 133 MHz 4 Banks × 4 Mbit × 16 LP-SDRAM P-VFBGA-54-2 HYB18L256160BCL-7.5 133 MHz 4 Banks × 4 Mbit × 16 LP-SDRAM P-VFBGA-54-2 HYB18L256160BF-7.5 133 MHz 4 Banks × 4 Mbit × 16 LP-SDRAM HYB18L256160BFL-7.5 1) HY[B/E]: Designator for memory products (HYB: Standard temp. range; HYE: extended temp. range) 18L: 1.8 V Mobile-RAM ...
Page 5
... Description The HY[B/E]18L256160B[C/F high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. The HY[B/E]18L256160B[C/F]L achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are burst- oriented ...
Page 6
... SELF REFRESH. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple memory banks considered part of the command code. RAS, CAS, Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. ...
Page 7
... Functional Description The 256-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command ...
Page 8
Power On and Initialization The Mobile-RAM must be powered up and initialized in a predefined manner (see those specified may result in undefined operation first, device core power ( ) and device IO power ( DD ...
Page 9
Register Definition 2.2.1 Mode Register The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency ...
Page 10
Burst Length READ and WRITE accesses to the Mobile-RAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. ...
Page 11
Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined ...
Page 12
... Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be restricted to variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by (cf. ...
Page 13
State Diagram Rev. 1.73, 2006-09 01302004-CZ2R-J9SE HY[B/E]18L256160B[C/F]L-7.5 13 Data Sheet 256-Mbit Mobile-RAM FIGURE 4 State Diagram ...
Page 14
... BA0, BA1 are reserved A12 provide the op-code to be written to the selected mode register. 9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read cycles; DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; ...
Page 15
Parameter Clock cycle time Clock frequency Clock high-level width Clock low-level width Address and command input setup time Address and command input hold time Rev. 1.73, 2006-09 01302004-CZ2R-J9SE HY[B/E]18L256160B[C/F]L-7.5 Address / Command Inputs Timing Parameters Symbol - 7.5 min. t ...
Page 16
NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to a Mobile-RAM which is selected (CS = LOW). This prevents unwanted commands from being registered during idle states. Operations already in progress are not ...
Page 17
MODE REGISTER SET The Mode Register and Extended Mode Register are loaded via inputs A0 - A12 (see mode register descriptions in Chapter 2.2). The MODE REGISTER SET command can only be issued when all banks are idle and ...
Page 18
ACTIVE Before any READ or WRITE commands can be issued to a bank within the Mobile-RAM, a row in that bank must be “opened” (activated). This is accomplished via the ACTIVE command and addresses A0 - A12, BA0 and ...
Page 19
READ Subsequent to programming the mode register with CAS latency and burst length, READ bursts are initiated with a READ command, as shown in Figure the DQs are shown in Figure 12; they apply to all read operations and ...
Page 20
Parameter Access time from CLK DQ low-impedance time from CLK DQ high-impedance time from CLK Data out hold time DQM to DQ High-Z delay (READ Commands) ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE to PRECHARGE ...
Page 21
Data from any READ burst may be concatenated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. A READ command can be initiated on any clock cycle following a previous READ ...
Page 22
Non-consecutive READ bursts are shown in Rev. 1.73, 2006-09 01302004-CZ2R-J9SE Figure 17. 22 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 16 Random READ Bursts FIGURE 17 Non-Consecutive READ Bursts ...
Page 23
READ Burst Termination Data from any READ burst may be truncated using the BURST TERMINATE command (see Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE command must be issued ...
Page 24
Clock Suspend Mode for READ Cycles Clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. As long as CKE is registered LOW, the following internal clock pulse(s) will be ignored ...
Page 25
READ - DQM Operation DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing parameters as listed in Table 12 also apply to this DQM operation. The read burst in ...
Page 26
READ to WRITE A READ burst may be followed by or truncated with a WRITE command. The WRITE command can be performed to the same or a different (active) bank. Care must be taken to avoid bus contention on ...
Page 27
READ to PRECHARGE A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that Auto Precharge was not activated. This is shown in The PRECHARGE command should be issued x clock ...
Page 28
WRITE WRITE bursts are initiated with a WRITE command, as shown in Figure 23. Basic timings for the DQs are shown in Figure 24; they apply to all write operations. The starting column and bank addresses are provided with ...
Page 29
Parameter DQ and DQM input setup time DQ input hold time DQM input hold time DQM write mask latency ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE to PRECHARGE command period WRITE recovery time PRECHARGE command ...
Page 30
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge of clock ...
Page 31
Non-consecutive WRITE bursts are shown in Rev. 1.73, 2006-09 01302004-CZ2R-J9SE Figure 29. 31 Data Sheet HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM FIGURE 28 Random WRITE Bursts FIGURE 29 Non-Consecutive WRITE Bursts ...
Page 32
WRITE Burst Termination Data from any WRITE burst may be truncated using the BURST TERMINATE command (see Precharge was not activated. The input data provided coincident with the BURST TERMINATE command will be ignored. This is shown in Figure ...
Page 33
Clock Suspend Mode for WRITE Cycles Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long as CKE is registered LOW, the following internal clock pulse(s) will be ignored ...
Page 34
WRITE - DQM Operation DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be performed. The generic timing parameters as listed in Table 13 and will continue as ...
Page 35
WRITE to READ A WRITE burst may be followed by, or truncated with a READ command. The READ command can be performed to the same or a different (active) bank. With the registration of the READ command, data inputs ...
Page 36
BURST TERMINATE The BURST TERMINATE command is used to truncate READ or WRITE bursts (with Auto Precharge disabled). The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in Figure ...
Page 37
PRECHARGE The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a t specified time ( ) ...
Page 38
Parameter ACTIVE to PRECHARGE command period WRITE recovery time PRECHARGE command period 1) These parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; ...
Page 39
Rev. 1.73, 2006-09 01302004-CZ2R-J9SE HY[B/E]18L256160B[C/F]L-7.5 READ with Auto Precharge Interrupted by WRITE WRITE with Auto Precharge Interrupted by READ 39 Data Sheet 256-Mbit Mobile-RAM FIGURE 38 FIGURE 39 ...
Page 40
AUTO REFRESH and SELF REFRESH The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways explicit AUTO REFRESH command internally timed event in ...
Page 41
SELF REFRESH The SELF REFRESH command can be used to retain data in the Mobile-RAM, even if the rest of the system is powered down. When in the self refresh mode, the Mobile-RAM retains data without external clocking. The ...
Page 42
Parameter ACTIVE to ACTIVE command period PRECHARGE command period Refresh period (8192 rows) Self refresh exit time 1) These parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = ...
Page 43
POWER DOWN Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power- down; if power-down occurs when there is ...
Page 44
... The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current consumption. Deep power down mode is entered using the BURST TERMINATE command (cf. internal voltage generators inside the device are stopped and all memory data is lost in this mode. To enter the deep power down mode all banks must be precharged. ...
Page 45
READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and READs or WRITEs with Auto Precharge disabled. 10) May or may not be bank-specific; if multiple banks are to be precharged, each ...
Page 46
Current State CS RAS CAS Any Idle Row Activating Active Precharging Read (Auto Precharge L ...
Page 47
Idle The bank has been precharged, and Row Active A row in the bank has been activated, and register accesses are in progress Read A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or ...
Page 48
Electrical Characteristics 3.1 Operating Conditions Parameter Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Attention: Stresses above those listed here may cause permanent ...
Page 49
Parameter Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input high voltage Input low voltage I Output high voltage ( = -0.1 mA Output low voltage ( = 0.1 mA) OL Input leakage current Output leakage ...
Page 50
Parameter DQM write mask latency ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B delay ACTIVE to PRECHARGE command period WRITE recovery time PRECHARGE command period Refresh period (8192 rows) Self ...
Page 51
Operating Currents Parameter & Test Conditions Operating current: one bank: active / read / precharge Precharge power-down standby current: all banks idle, CS ≥ CKE ≤ V IHmin ILmax inputs changing once every two ...
Page 52
Parameter & Test Conditions Max. Temperature 85 °C Self Refresh Current: Self refresh mode, 70 °C full array activation 45 °C (PASR = 000) 25 °C 85 °C Self Refresh Current: Self refresh mode, 70 °C half array activation 45 ...
Page 53
Pullup and Pulldown Characteristics Voltag Half Drive Strength e (V) Pull-Down Current (mA) Pull-Up Current (mA) Nominal Nominal Nominal Low High Low 0.00 0.0 0.0 -19.7 0.40 15.1 20.5 -18.8 0.65 20.3 28.5 -18.2 0.85 22.0 32.0 -17.6 1.00 ...
Page 54
Package Outlines 0 Marking Ballside 2) Die Sort Fiducial 3) Bad Unit Marking (BUM) 4) Middle of Packages Edges 5) Middle of Ball Matrix Rev. 1.73, 2006-09 01302004-CZ2R-J9SE P-VFBGA-54-2 (Plastic Thin Fine Ball ...
Page 55
List of Figures Figure 1 Standard Ballout 256-Mbit Mobile-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 56
Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 57
Pullup and Pulldown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 58
Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ...